ePIC pfRICH electronics mailing list

["Kiselev, Alexander" <ayk AT bnl.gov>]

  Hi Gabor,

  An interesting collection. Looks like we need KFH studs with custom spacers? Or perhaps KFE / KRB3 if they can withstand the force.

  Cheers,

    Alexander.

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From: nagy g <hunagabo AT gmail.com>
Sent: Thursday, August 3, 2023 12:36 PM
To: Kiselev, Alexander <ayk AT bnl.gov>
Cc: Cacace, Daniel <dcacace AT bnl.gov>; czeller.miklos AT gmail.com <czeller.miklos AT gmail.com>; Damien Thienpont (IN2P3) <damien.thienpont AT in2p3.fr>; Pierrick Dinaucourt <pdinaucourt AT omega.in2p3.fr>
Subject: Re: pfRICH prototype HGCROC3 ASIC & FPGA cooling scheme

 

Hi Alexander,

I agree and sure we can go further to work out the details, but I would appreciate, if Daniel (?) could add the mating connectors to the mechanical model (like Ethernet) just to see if they can be connected with the tiling setup as well. (even the connectors within the base PCB contour.)

But basically I am happy with this configuration as it seems to be feasible.

The model what I sent is created by Miklos, so I will do my own one and will add the solderable standoffs or the pressfit bolts (based on what is available).

https://appianfasteners.com/media/downloads/kdata.pdf 

Br, gabor

Kiselev, Alexander <ayk AT bnl.gov> ezt írta (időpont: 2023. aug. 3., Cs, 13:54):

  Hi Gabor,

  sure, vertical connector orientation makes tiling easier, to articulate the case. One of Daniel's pictures (with a blue fan superimposed with a sink) shows that there is no conflict with cabling either. Should we "freeze" this layout, and work out the remaining details based on it? I see Samtec connectors and FPGA itself are already placed symmetrically with respect to the ASICs in this picture as well. Heat sink should probably be a single piece, do we agree? There is no conflict with HV pins / cables. Then what is missing, from the mechanical / integration standpoint is: (1) screws which fix ASIC board on the sensor and a fiducial volume around the respective nuts, (2) pressfit fixtures to bolt two PCBs together, (3) whatever is needed to fix the sink assembly on top of everything else. Anything else?

  As far as I understand, once we all agree on such a configuration in general, Daniel can work out a heat sink layout, decide on the Samtec connector height, and we think about sensor assembly mounting scheme as a whole on our end, while ASIC board and FPGA board design get decoupled from each other once the Samtec connector pins are assigned, and LV scheme is decided upon. Correct?

  By the way, my gut feeling is that in the real detector setup all connectors will be oriented horizontally, since it is the space in the direction normal to the sensor plane which is at a premium. As long as the connectors themselves are within the sensor footprint, cables can always be disconnected to take a neighboring sensor out. My 2 cents.

  Cheers,

    Alexander.

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From: nagy g <hunagabo AT gmail.com>
Sent: Thursday, August 3, 2023 6:40 AM
To: Cacace, Daniel <dcacace AT bnl.gov>
Cc: Kiselev, Alexander <ayk AT bnl.gov>; czeller.miklos AT gmail.com <czeller.miklos AT gmail.com>; Damien Thienpont (IN2P3) <damien.thienpont AT in2p3.fr>; Pierrick Dinaucourt <pdinaucourt AT omega.in2p3.fr>
Subject: Re: pfRICH prototype HGCROC3 ASIC & FPGA cooling scheme

 

Hi Daniel and Alexander,

The reason I proposed the straight connectors (vertical connection) was to allow the detector to put next to each other in all 4 direction. With the right-angle connectors (connecting from sides) it will be limited, but I do not know the application deep enough...

So, if that is acceptable then we can go that direction. From the PCB point of view that is not a big deal :)

(just one comment, I would still prefer to use one big metal plate as a base of the heat-sink, instead of 3 separated one. Just to keep the module assembly simple.)

Br. gabor

Cacace, Daniel <dcacace AT bnl.gov> ezt írta (időpont: 2023. aug. 2., Sze, 20:02):

I realize this is missing the Samtec connector, but something more along these lines would be preferable.

Dan Cacace
sPHENIX
Physics Department
Office: 631.344.2197
dcacace AT bnl.gov

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From: Cacace, Daniel <dcacace AT bnl.gov>
Sent: Wednesday, August 2, 2023 1:56 PM
To: Kiselev, Alexander <ayk AT bnl.gov>; nagy g <hunagabo AT gmail.com>
Cc: czeller.miklos AT gmail.com <czeller.miklos AT gmail.com>; Damien Thienpont (IN2P3) <damien.thienpont AT in2p3.fr>; Pierrick Dinaucourt <pdinaucourt AT omega.in2p3.fr>
Subject: Re: pfRICH prototype HGCROC3 ASIC & FPGA cooling scheme

 

Hi Alexander and Gabor,

I agree, with the full heat sink and fan I was confident the cooling would be sufficient. Without having done any calculations, something like you show in your images I think would be marginal with a fan and probubly insufficient without a one.

I was thinking the same thing as Alexander, that a longer FPGA board would be better. Here are few images of what I would propose. Does it look reasonable? I show the heat sink in 3 sections, but it could be one part with a few cutouts, though I don't think it would really affect the cooling.

Thanks,

Dan Cacace
sPHENIX
Physics Department
Office: 631.344.2197
dcacace AT bnl.gov

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From: Kiselev, Alexander <ayk AT bnl.gov>
Sent: Wednesday, August 2, 2023 1:41 PM
To: nagy g <hunagabo AT gmail.com>
Cc: czeller.miklos AT gmail.com <czeller.miklos AT gmail.com>; Damien Thienpont (IN2P3) <damien.thienpont AT in2p3.fr>; Pierrick Dinaucourt <pdinaucourt AT omega.in2p3.fr>; Cacace, Daniel <dcacace AT bnl.gov>
Subject: Re: pfRICH prototype HGCROC3 ASIC & FPGA cooling scheme

 

  Hi Gabor,

  thank you, I can download the STEP file. Are you really suggesting to proceed without even a fan? Otherwise RJ45 cable sticking out vertically seem to become a problem. I'd still see it more natural to have a longer FPGA board, with all three cables routed away horizontally (like in your first iteration), and ERM5 connectors places symmetrically with respect to their respective ASICs (so neither the way the ones below the FPGA board are located nor the ones which are seen on the open half of the board). Also, one can still have a giant single heat sink with a fan even if it covers a pair of FPGA boards. 

  Daniel, will you have time to come up with a scheme which would take the best of the proposals made so far, from the cooling perspective?

  Cheers,

    Alexander.

 

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From: nagy g <hunagabo AT gmail.com>
Sent: Wednesday, August 2, 2023 10:58 AM
To: Kiselev, Alexander <ayk AT bnl.gov>
Cc: czeller.miklos AT gmail.com <czeller.miklos AT gmail.com>; Damien Thienpont (IN2P3) <damien.thienpont AT in2p3.fr>; Pierrick Dinaucourt <pdinaucourt AT omega.in2p3.fr>; Cacace, Daniel <dcacace AT bnl.gov>
Subject: Re: pfRICH prototype HGCROC3 ASIC & FPGA cooling scheme

 

just two correction (from Miklos :)):

- STEP model available here: https://web.tresorit.com/l/ZObME#B37XtULDHJE9ocNaJ999nw

- And the connector on the board is a 60 pin version (ERM5-030-05.0-L-DV-TR)

Br, gabor

nagy g <hunagabo AT gmail.com> ezt írta (időpont: 2023. aug. 2., Sze, 15:47):

Hi Alexander,

- The PEMs are not in the model jet (around the connectors), but the rest shows what we discussed last time.
- Heat sink plate (horizontal part of it) is covering the ASICs directly, and the size is the same as the PCB itself to enable putting the detectors next to each other.

- The vertical part of the heat-sink needs additional work as well, but again, it is just a quick model to explain the possibilities.

- Regarding the connectors, the 40-pin version of SAMTEC's ERM5 series connector is used for the model to make sure the power can use multiple pins. (ERM5-020-05.0-L-DV-TR)

The STEP file is ~5MB so I would not attach it to the mail, but if you can send me any place to upload it, I can do that.

(With one note for the model! As we have no model for the ASIC and the carrier board, all sizes are just approximately measured back from the slides you shared with us... so do not expect them to be correct.)

Best Regards, gabor

Kiselev, Alexander <ayk AT bnl.gov> ezt írta (időpont: 2023. júl. 31., H, 18:59):

  Hello colleagues,

  in the meantime, would it be possible to share a CAD model a la slide 9 here https://indico.bnl.gov/event/20090/contributions/78664/attachments/48726/82859/ayk-2023-07-20-erd110-meeting.pdf with Daniel (Cc), with a ~4cm wide FPGA board and ASICs swapped with the Samtec connectors, so that they are not shadowed by the FPGA boards? Daniel will then distribute an update of a cooling solution for the prototype.

  Thank you,

     Alexander.