ePIC pfRICH electronics mailing list

["Kiselev, Alexander" <ayk AT bnl.gov>]

  Dear Pierrick, Gabor,

  see all I have about the Y05f (passive HRPPD interface board) attached: a STEP model, a snapshot of this model in a CAD viewer, a picture of  a real bare board with a pair of ERF8 connectors on top of it, and - for completeness - a gerber file set.

  Small pinholes in the CAD model are "fake". They just confirm the center locations of the 16 8x8 pad fields with a pitch of 2mm. The bottom side of the ASIC board should look exactly the same as you see this in the Y05f picture (except for the ERF8 alignment holes), with the ground picture frame squares around each of the sixteen 8x8 pad fields.

  The ASIC board should have no active or passive components on its bottom (pad) side.  If they are absolutely needed, their profile should be less than 1.0mm, and we will have to carve a 3D printed spacer around them accordingly.

  Stay clear area around all mechanical holes on the top side of the ASIC board should be 7mm diameter. If this is unacceptable, let's discuss this once again with Daniel and Gabor.

  We should avoid using components which would not work in a magnetic field (like transformers). Sooner or later somebody will suggest to perform an HRPPD test with this ASIC backplane in a magnetic field.

  Cheers,

    Alexander.

Attachment: Y05f.stp
Description: Y05f.stp

Attachment: Y05f.CAD.png
Description: Y05f.CAD.png

Attachment: Y05f.png
Description: Y05f.png

Attachment: Y05f.zip
Description: Y05f.zip