ePIC pfRICH electronics mailing list

[Christophe de La Taille <taille AT in2p3.fr>]

dear all,

looking at the boards and schematics with Pierrick and Damien, we are a bit worried to use the same connector for the direct ASIC power supply and for the FPGA as a risk of bringing 5V to the ASICs if plugged in the wrong place, this would destroy all the chips.  We could use 2x2 and a 1x4 in the different locations to minimize this risk or avoid mounting them on the ASIC board if the powering via FMC/FPGA board is OK.

The DCDC convertor can also be a source of noise as the chips inputs are very sensitive. On CMS hexaboards, the convertors have to be shielded and we saw on the noise the place where there was a hole in the shield... Facing the chips rather than the outside may also increase the risk of noise coupling.  Providing possibility of mounting a shield, thoroughly connected to ground would be useful.

The heat dissipation of both DCDC and linear regulators may also be an issue, are you confident that they will not overheat ?

Probably we can proceed as it is now in order not to delay the schedule and keep it for next version.

Best regards :  Christophe

On 14/11/2023 15:43, Kiselev, Alexander via Eic-projdet-pfrich-electronics-l wrote:

          Hello colleagues,
      
        
      
      
          attached is r14, with the recent corrections by Gabor
        implemented, and hyperlinks working.
      
        
      
      
          Please provide your feedback by tomorrow Wednesday. I'd also
        appreciate if people address the highlighted items by the end of
        this week, except for sections 5 & 6.
      
        
      
      
          Regards,
      
            Alexander.

---

From: Kiselev, Alexander
Sent: Monday, November 13, 2023 2:59 AM
To: Camarda, Timothy via Eic-projdet-pfrich-electronics-l <eic-projdet-pfrich-electronics-l AT lists.bnl.gov>
Subject: HRPPD HGCROC backplane interface document r12

 

  Hello colleagues,

            r12 with the modifications following our Friday meeting is
          attached. I believe I incorporated all comments, and also
          uploaded all new materials.
        
          
        
        
            Missing items are color coded: magenta (AK), red (Pierrick),
          cyan (Gabor), yellow (Miklos), green (Daniel). Some of them
          require more work to converge.
        
        
          
        
        
            Daniel: once Pierrick provides his CAD
          model, please perform a final consistency check, at which
          point one can start finalizing the cooling system
          configuration.
        
        
          
        
        
            All those with experience in schematics (but Pierrick
          in particular): please consider providing your feedback to the
          FMC board package revision r03 which Gabor sent out yesterday
          (it is also linked from the attached pdf file), by Wednesday.
        
        
          
        
        
            Regards,
        
              Alexander.
        
          
        
        
          
        
      
      
      
    
-- 
--
Christophe de LA TAILLE
OMEGA CNRS/IN2P3 Micro-Electronics Design Lab
Professor of micro-electronics at Ecole Polytechnique
Ecole Polytechnique  F91128 Palaiseau France
+33 16933 8998