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[Eic-projdet-pfrich-electronics-l] HRPPD HGCROC3 FPGA interface board V0

From: "Kiselev, Alexander" <ayk AT bnl.gov>
To: "Camarda, Timothy via Eic-projdet-pfrich-electronics-l" <eic-projdet-pfrich-electronics-l AT lists.bnl.gov>
Subject: [Eic-projdet-pfrich-electronics-l] HRPPD HGCROC3 FPGA interface board V0
Date: Wed, 20 Mar 2024 19:28:53 +0000

Hello colleagues,

We were kindly asked by the EIC Project management to send any essential e-mail to the respective mailing lists rather than to a subset of individuals. Let's follow this practice from now on.

I'm just back from the PCB shop here on LI, and what you see in the bottom half of the attached picture is the HRPPD FPGA V0 board (attached to the ASIC board in a half without chips, just to take a picture). We are hopefully one step closer in building this interface for the HRPPD / pfRICH evaluation while waiting for EICROCs.

Should probably wait until we make sure this combo actually works, yet let me congratulate everybody with this milestone! On a hardware side, it essentially concludes the V0 stage of this design.

Cheers,

Alexander.

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[Eic-projdet-pfrich-electronics-l] HRPPD HGCROC3 FPGA interface board V0, Kiselev, Alexander, 03/20/2024