Sphenix-tpc-l mailing list

["Huang, Jin" <jhuang AT bnl.gov>]

Many progresses following the last meeting 10 days ago. Minutes also available on agenda page: https://indico.bnl.gov/conferenceDisplay.py?confId=2653

 

 

Announcement:

Next TPC DAM meeting will be Wed Jan 18 11AM-12PM @ 2-160.

 

 

Action Items:

 

·       PCIe test board setup: We plan to formally request one spare v1.5 FELIX PCIe card early next year to establish a test stand.

·       John K.: look into evaluation board to simulate sPHENIX clock and FEE data output for PCIe card testing.

·       John K. + Jin: define internal data format in DAM

·       Jin: analyze HIJING simulation to quantify fluctuation of hit data stream. Request send to Chris for HIJING production.

·       Raw data compression: after raw data defined, we will run CPU test first

·       Takao: archive schematics for STAR iFEE.

·       Martin: define raw output data format.

 

 

Invited talk: Introduction to ATLAS FELIX readout system - Kai Chen, BNL/Omega group

 

Michael Begel: this system to be used in ATLAS phase I upgrade, which is projected to complete before sPHENIX. Local expert available for help. The team is also help in possible use of FELIX card in protoDune. The FELIX team is open for inputs in guiding the design to be more generic to various users.

 

Slide 3:

Kai: each 96 port can be configured separately for protocol and speed.

 

Slide 7:

John K.: Which DMA mode is used?

Kai: DMA core is on OpenCores, rather than from XLinux.  

 

Slide 18:

Kai: TTC is ATLAS clock trigger distribution

 

Slide 22:

Wei Lu: What will be the global clock speed?

Kai: FELIX uses 320 MHz, while it was tested up to 560 MHz

 

Slide 24:

Michael /Kai: the ATLAS group can help design sPHENIX TPC timing mezzanie.

Kai: the FELIX PCIe board was layout by Instrumentation.

 

Slide 8:

Phase 1: Phase I upgrade long shutdown starts Jan 2019. Meanwhile, FELIX will be used earlier in prototyping and test beam of a few subsystem. Production system delivery expected end 2018, needing 100+ card with various flavor of firmware depending on subsystem configurations.

 

Slide 20: considerations for sPHENIX TPC user

·       buffer size looks promising for TPC hit buffering.

·       Commercial IP found to implement FPGA based compression if needed

 

Slide 25: production schedule FELIX PCIe card v2.0

 

Slide 26: help that ATLAS group can offer if sPHENIX TPC user FELIX card

·       Boards after the initial evaluation test.

·       Support of the reusable firmware & software development from current designs.

·       Help design the mezzanine card for the special timing system.

·       Additional hardware functions if compatible with the FELIX project.

 

 

SAMPA format - Takao

 

Slide2:

Takao: Cluster size and Time count are both in 10-bits

Takao: bit counts from left to right

John K.: BX is beam crossing clock count

 

Slide 3:

Mike: what will be the protocol between FEE->DAM?

Takao: not yet designed

 

Slide 4:

Takao: Cluster is one set of continuous signal in ADC samples

John K.: each channel has dedicated ADC

 

Slide 5: the DAQ design parameter 5x3 sample/cluster should be the max data case. Expect less data in reality.

 

 

Updated DAQ diagram - Jin Huang

 

Introduction:

Would CD-1 review delayed by continuous resolution? Maybe not.

Maybe FELIX can be sold to ALICE?

 

Slide 5:

John K. 40GB Ethernet could be used. This would be great.

 

Slide 6:

Typo, FELIX card uses Kintex Ultrascale

 

Slide 7: Trigger will be transferred by fiber too.

 

Slide 8: 4.8Gbps data rate --> 3.2Gbps payload rate.

 

Slide 9: Keeping the memory is an option to explore

 

New slide 10: (missing slide during presentation)

Triggering mode only output 10% relatively more duplicated data when comparing to the throttling mode, but give benefit of analysis and monitoring.

 

Slide 11:

Martin: assuming 60% reduction by LZO is not very trivial due to the compactness of TPC data comparing to PHENIX data. We have to be careful about the number a bit.

Jin: maximum continuous rate of 19Gbps is for most inner module. The data from the most inner radius can be split to two or more servers.

Takao: Sidemark, FEE card have to be made FPGA reprogrammable through optical fiber.

 

Slide 12: FPGA on DAM just do trigger association, timing alignment.

 

Worrisome for the effect of bit error in FPGA to the compressed event?

 

40Gbps dump rate is net payload rate of 1008 -> RCF.

 

Fake data for rate evaluation will be produced by Takao S. soon.

 

 

Exploring ideas of FEE/DAM protocols - John Kuczewski

 

1.       Exploring two possible protocol between FEE->DAM: 8b10b and UDP

2.       Thoughts on using the DDR4 memory on FELIX v1.5 card

3.       SAMPA data format documentation.

 

Section 1:

·       John: trying to padding to fit in particular protocol.

·       A FEE card address and association with the position is needed in the UDP case.

 

Section 3:

·       Find out SAMPA Register. John H. have a spread sheet.

·       RHIC Clock is 9.4 Mhz. Expect SAMPA sampling rate is sync to RHIC clock at 9.4 MHz too.

 

How many thresholds one can set for one SAMPA? one THRES/channel? TS will check the slow control bits.

 

 

 

 

 

 

 

 

______________________________

 

Jin HUANG, Ph. D.

 

Associate Physicist

Brookhaven National Laboratory

Physics Department, Bldg 510 C

Upton, NY 11973-5000

 

Office: 631-344-5898

Cell:   757-604-9946

______________________________

 

From: Huang, Jin
Sent: Friday, December 16, 2016 11:30 AM
To: 'sphenix-tpc-l AT lists.bnl.gov' <sphenix-tpc-l AT lists.bnl.gov>
Cc: 'sphenix-maps-l AT lists.bnl.gov' <sphenix-maps-l AT lists.bnl.gov>; Mead, Joseph <mead AT bnl.gov>; Sakaguchi, Takao <takao AT bnl.gov>; 'Cheng-Yi Chi' <chi AT nevis.columbia.edu>; Purschke, Martin <purschke AT bnl.gov>; Haggerty, John <haggerty AT bnl.gov>; 'Klaus Dehmelt' <klaus.dehmelt AT stonybrook.edu>; 'Tom Hemmick' <hemmick AT rcf.rhic.bnl.gov>; Chen, Kai <kchen AT bnl.gov>; Chen, Hucheng <chc AT bnl.gov>; 'Ming X. Liu' <ming AT bnl.gov>; Da Silva, Cesar <slash AT bnl.gov>; Smith, Graham <gsmith AT bnl.gov>; Fried, Jack <jfried AT bnl.gov>; Lu, Wei <wlu AT bnl.gov>; O'Brien, Edward <eobrien AT bnl.gov>; Kuczewski, John <jkuczewski AT bnl.gov>; Begel, Michael <begel AT bnl.gov>
Subject: [reminder] sPHENIX TPC DAM development meeting, Monday Dec 19, 3-4:30 PM @ 510C 2-160

 

Hello Everyone,

 

This is a reminder for the next sPHENIX TPC DAM development meeting, coming Monday Dec 19, 3-4:30 PM @ 510C 2-160.

 

The agenda is  https://indico.bnl.gov/conferenceDisplay.py?confId=2653 , which consists of three items:

1.       Update on specs and diagrams for the TPC DAQ

2.       Invited talk from Kai Chen to introduce ATLAS FELIX PCIe card, which may be of interest to the MAPS silicon detector group too.

3.       Plan on next month

 

For remote participants, please join via Browser:  https://bluejeans.com/530634249/browser

To join via phone :

1)  Dial:

                  +1.408.740.7256

                  +1.888.240.2560

                  +1.408.317.9253

                  (see all numbers - http://bluejeans.com/numbers)

2)  Enter Conference ID : 530634249

 

We are also planning the next*next meeting on Wednesday Jan 18, 11 AM-12 PM. Please mark your agenda too.  

 

Looking forward to talking to you,

 

 

Cheers,

 

Jin & Takao

 

______________________________

 

Jin HUANG, Ph. D.

 

Associate Physicist

Brookhaven National Laboratory

Physics Department, Bldg 510 C

Upton, NY 11973-5000

 

Office: 631-344-5898

Cell:   757-604-9946

______________________________