sPHENIX tracking discussion

[nouicer <rachid.nouicer AT bnl.gov>]

Dear Eric,

> To follow up on Ed's question, what is the inventory of working SPIRO boards and FEMs for the PIXEL system?

We have some documents of inventory of pixels elements and their locations. Your are author of the technical document of pixel tracker, and I am sure you will make sure that we have the right information in the technical note.  

>Also in looking at your slides it appears that you have added an additional bus extender to the end of the current extender.

No, what we have right now on the drawing/slide, it is exactly what we have in VTX. The exact length and thickness of existing readout bus and bus extender. For a longer bus extender option, I know there is a plan to discuss with the company in Japan. Right now, the question is there an issue with length of the existing bus extender, in order we can start explorer a longer bus? 
 
My focus now moves to build first prototype silicon tracker module. We need to see the signal.  
 
Thanks for these questions and I agree with your concerns. I am sure that you are the right person to carry out the challenges and solve problems for a longer bus extender because you know the issues. On top of that from your e-mail, I understand that you are volunteering 

Sincerely,
Rachid

On 04/15/2016 07:23 PM, Eric Mannel wrote:

Rachid-

To follow up on Ed's question, what is the inventory of working SPIRO boards and FEMs for the PIXEL system?

Also in looking at your slides it appears that you have added an additional bus extender to the end of the current extender.  All the digital I/O  with the the ALICE pixel chip are GTL (Gunning Transceiver Logic, which is  single ended) signals.  GTL was designed for what we now think of as moderate speed (10s of MHz)  and backplane (<1m distance) communications.  Has there been any discussion with an electrical engineer about what the limitations are on the distance of the bus extender and signal integrity for this type of signal over your proposed ?

Eric

On 04/15/2016 04:56 PM, EdwardOBrien wrote:

        HI Rachid,
          I have a couple of questions about the slides that you showed at the
    sPHENIX Tracker meeting today. Your slides show that when specific
    radii and ladder tilt angles are chosen for pixel layer P0 and P1
    you need 32 working ladders plus spares. My understanding is that
    the current PHENIX VTX has 30 ladders, of which ~ 40% have large
    dead areas.  What would be the plan to fully populate the sPHENIX
    vertex tracker with good working ladders?
     Also I am sure that in your last slide you meant that the first step
    of VTX integration into sPHENIX is done. A 3-D model of
     VTX ladders floating free in space as you showed is just the very
    start of Integration. But I'm sure that you know that. Thanks.


    Ed

    

On 4/14/2016 11:15 AM, Frawley, Anthony wrote:

HI All,

We will have an sPHENIX tracking meeting tomorrow, Friday April 15, at 9:00 am ET. The Indico page is:

https://indico.bnl.gov/conferenceDisplay.py?confId=200

The agenda is still clarifying.

In addition to reports on the detector options, I would like to have a general discussion about what is needed to meet the ALD's charge on detector cost. Mainly I would like to discuss what we will need to do to characterize the physics deliverd by tracking options, and how we will do it.

Cheers

Tony

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                                              /                       /
 Rachid Nouicer                              /                       /
 Physicist                                  /                       /
 Brookhaven National Laboratory (BNL)      /                       /
 Physics Department, Building 510c        /                       /
 20 Pennsylvania Avenue                  /                       /
 Upton, New York, 11973, U.S.A.         /Phone: +1 631 344 8433 /
 E-mail : rachid.nouicer AT bnl.gov       / Fax: : +1 631 344 3253/
 Web:http://www4.rcf.bnl.gov/~nouicer /                       /
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