sPHENIX tracking discussion

[Takao Sakaguchi <takao AT bnl.gov>]

Dear All,

 Thanks to those who participated the TPC electronics meeting
today. It was very productive. Here we send the memo from the
meeting.

Jin and Takao
-------------------

1, FEE connector to the pad plane should be selected. Joe will
pick several candidates and inform Tom and Klaus of them.

- The input signal comes individually (not paired with GND)
- There are bunch of GND lines separately.


2, Need an EEPROM for FPGA program download on FEE

- We might need JTAG or something to remotely reprogram
the EEPROM. Joe has some idea on this.


3, Design pre-prototype and prototype v1 FEE a.s.a.p.

- Schedule wise, completing prototype v1 by July is too tight.
- Let's shoot September for .prototype v1 completion


4, We may want to use real GEM signal from Bob Azmon's
setup for the Input signal to pre-prototype FEE

- Input connector should be properly chosen.
- pre-prototype may not meet the magnet test in June.


5, Based on the radiation estimated, the FPGA on FEE can
tolerate ~4-5 years of 24/7 running.

- 10uGy/sec @100KHz maximum
 --> 1mrad/sec @100KHz
 --> 30krad/year @100KHz, no downtime

- This is quoted for ionizing radiation. Neutron probably need a
separate estimation.


6, Seriousness of common mode noise found by ALICE for
sPHENIX TPC case

- Interaction rate and C_p are the key parameters to increase
(reduce) the noise.

- Tom and Klaus will evaluate in some way with some help
from Bob.


7, prototype v1 FEE spec

- connect all of e-link lines (11 from each SAMPA) to FPGA
with one SFP optical module.
- Two SFP mode can be tested with pre-prototype board.


8, FPGA occupancy check

- John will check how much logic will be consumed by:
a) simple common noise subtraction algorithm
b) conventional data compression algorithm
(as outlined on slide 9 by TS)

- Note that we deal with 320 Mbps serial data from SAMPAs.


9, Test Stand discussion

- We would need two type of pulse distribution board:
a) a board for a single FEE board
b) a board for 25 FEE board.

- We may need to start designing the a) board.

- Test scheme:
1) DAM module can be tested one-by-one using Artix-7
evaluation board
2) Basic test (voltage, on/off,etc) for FEE card will be
performed one-by-one.
3) 25 FEEs will be combined with a DAM module and then
tested as a readout chain

(1)-(3) will be one test cycle. We have to do 30 test cycles.


10,  DAM update

- The plan is to test FELIX card that will become available today

- Adding cluster fitting capability to DAM FPGA design. With an
estimated 50% data reduction ratio after cluster fit, the expected
TPC data rate to buffer box is ~80 Gbps with all cluster fitted.

- It is very nice to keep unfit and fit output (clustering)

-- 
Takao Sakaguchi
Brookhaven National Laboratory
Physics Department, Bldg. 510C
takao AT bnl.gov
Office: 1-631-344-3345