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[Gerard Visser <gvisser AT indiana.edu>]

hi Flemming,
	That is correct, 36 inner cables. We will have one cable per silicon module 
(wedge) assembly, which is 8 APV chips. 3*12 such modules.
	There is in the module and inner cable a separate bias "HV" for inner and 
outer. These will be tied at the patchpanel board, but could be separated later 
if there was need.
	We need 36 patchpanel boards, being 3 assemblies of 12 patchpanel boards, half 
of IST, which is exactly what we have (other half is lost, it seems).
	We need 36 outer cables, and 18 ARM's (we have 36 + spares at IU - a few in 
test systems), no problem.
	We need 6 ARC-II, and all 3 IST readout crates. In principal we could use half 
as many as you say, but by keeping to 6 we maximize the rate capability / 
minimize deadtime. The crate now in Prithwish's lab will be *the* spare. (We 
never had to swap crates or powerboxes in past for FGT/GMT/IST, as far as I 
recall, but we better keep this spare on hand.)
        Hopefully this makes sense... Sincerely,

                Gerard


On 10/9/2019 6:14 PM, flemming videbaek wrote:
> 10/9/2019
>
>
> A couple of updates and questions.
>
>   
> I am preparing a MS project file for the schedule of the FST. I have taken the information from the review with updates on schedules as presented in misc. presentation later. The implicit time scale for assembly work at FNAL has been included. As the schedule so far is mainly milestones for completion, there will be several open questions that needs to be answered. I plan to send these around to relevant people in the next week or so. The skeleton for this is about 80% done.
>
>
> The order for the epoxy etc. for the assembly of prototype has been placed in 
> the BNL system. It will be delivered to BNL and then shipped to FNAL. Three 
> of 4 items is stock, but one component has an expected 3 week delivery. 
> Likely ~4 weeks in total from now.
>
>
> I like to have confirmed that only 36 inner cables are indeed needed. This 
> implies that for one wedge the HV controls one inner and two outer sensors, 
> and that we only need to use half of the existing IST ARM/ARC crates. I also 
> note that the latest drawing from Rahul/John with the cable/cooling routing 
> does not use the latest layout of the wedges and the cooling. Have BNL gotten 
> the latest version of CAD model? The routing of the cooling and cables should 
> be worked on.
>
>
>
> Flemming Videbaek
> senior scientist
> videbaek @ bnl.gov
> Brookhaven National Lab
> Physics Department
> Bldg 510D
> Upton, NY 11973
>
> phone: 631-344-4106
> cell     :  631-681-1596
>
>
>
>
>
>
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