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[Gerard Visser <gvisser AT indiana.edu>]

Hi Xu,
	Do you have a dataset that could be used to make a plot of noise vs. bias 
similar to the left hand plot on your slide 10, for the two cases of:

- The channel (of a typical chip) which was the worst noise i.e. this would be 
one of the few anomalous channels.

- A single channel of same chip that shows the typical noise.

	This would show clearly if these anomalously noisy channels' noise are related 
to the frontend amplifier ( <==> related to detector capacitance) or not. For 
instances noise due to soe crosstalk from the digital header (perhaps from ADC 
timing wrong) should not have anything to do with detector capacitance. Noise 
that we may speculate coming from the power glitch that happens when readout 
starts, would similarly have nothing to do with detector capacitance.

	I suppose these plots are easiest and most meaningful without a CMN correction, 
simply the raw noise seen in pedestal on the channel as a function of detector 
bias as in that figure on slide 10.
        If it is not too hard to get such plots, I'd look forward to seeing 
them. Thanks,

        Gerard