U.S. ATLAS HL-LHC Upgrade LAr Level 2 and Level 3 Managers Mailing List

[Tim Andeen <timothy.robert.andeen AT cern.ch>]

No. 13: 

“…ultimate goals  were not met for the latest, v2, prototype. ”
With the v2 pre-prototype the primary goal was to integrate the individual blocks into a 2 channel ADC, testing it as a single LAr channel system, with on-chip digital processing and control and an e-link for lpGBT testing. As far as precision, this was an incremental step toward the ultimate precision goal and, though it would have been great to meet the ultimate goal in v2, we anticipated 3 pre-prototypes, before the final prototype (4 iterations). 

“v1 and v2 and what issues, so far, need to be addressed in a v3”
V1->v2 was a major step in integrating the DRE and SAR in a 2 channel design, with many changes. Looking forward, for v3 we had a 2 day workshop at UT Austin in April to address the challenges remaining.  In v3 the issues are the noise limiting the performance at the lowest energies, and the calibration of the 4x DRE gain, limiting the performance at the highest energies. In the DRE improvements will come through adding an on-chip gain calibration using a DAC ladder, and improvements in the sampling network to reduce kickback. In the SAR the improvements come through adding an additional physical bit in the second stage of the SAR, to improve the overall resolution to 11.5b, at the cost of additional power. 

“…what improvements to the performance, either in  hardware, software, or firmware can  we expect with the current v2 chip before the FDR.”
For the v2 chip we don’t anticipate any changes or improvements, testing the v2 on it’s own is effectively concluded (though still ongoing as part of the analog test board). The ATLAS FDR in December 2019 will focus on the results of the v3. 

No. 16:  

"Can you clarify how the calibration of the gain of the “4x” part of  the ADC relative to the “1x” part will be done?  What is the needed accuracy on this calibration? "
   The calibration of the DRE will done by including a resistive DAC ladder on the chip, and an algorithm implemented in digital circuits on chip. This I a 5-bit calibration, accurate to within 0.01 (on a gain of ~4), design for 0.005 accuracy.
   As an alternative, an MDAC is also being implemented in v3. This has the advantage of simplifying the overall architecture, and reuses many of the  blocks of the DRE.  

On Mon, Jul 29, 2019 at 11:09 PM John Parsons <parsons AT nevis.columbia.edu> wrote:

FYI.  In round 2, we have a number of LAr-specific
questions to address.  They are all about FE, so I suggest
Tim handles preparing short written responses to 13, 16,
18, 19 and I will handle the rest.

If we all meet at 9 am tomorrow, we will have an hour
to go over things before our 10-12 session, and then
more time over lunch before the Q&A session at 1:30.

                John

-------- Forwarded Message --------
Subject:        [Usatlas-hllhc-l2deputymgmt-nsf-l] FW: Questions Part B
Date:   Tue, 30 Jul 2019 02:34:02 +0000
From:   Michael Tuts <tuts AT pmtuts.net>
To:     usatlas-hllhc-pomgmt-l AT lists.bnl.gov
<usatlas-hllhc-pomgmt-l AT lists.bnl.gov>,
usatlas-hllhc-l2deputymgmt-nsf-l AT lists.bnl.gov
<usatlas-hllhc-l2deputymgmt-nsf-l AT lists.bnl.gov>



Hi L2’s,

Please pass on the L3s as well.

Mike

*From:*Daniel R. Marlow <marlow AT Princeton.EDU>
*Sent:* Monday, July 29, 2019 10:30 PM
*To:* Michael Tuts <tuts AT pmtuts.net>
*Cc:* Denisov, Dmitri <denisovd AT bnl.gov>; Coles, Mark W.
(mcoles AT nsf.gov) <mcoles AT nsf.gov>
*Subject:* Questions Part B

Hi Mike,

     Please find a more extensive set of questions comprising the “Part
A” questions from before

(which remain the same) plus an additional set of “Part B” questions.   
Although these arrive late, the answers aren’t “due” until after lunch
tomorrow, so I trust you will have time to prepare them.

Cheers,

Dan

Questions for ATLAS

1) It is understood that the variance analysis is not yet being posted
to IPD.   It would,

     however, be useful to see what you have collected thus far (in any
convenient format).

2) The June monthly report says that the EV report has bugs.   Please
explain the origin of the

     problem.   Is it e.g., related to the tool being used or the data.

3) The EAC reported in the June report is not same as the BAC. What is
the primary reason

     for this?

4) In the subsystem presentations two contingency  numbers were usually
given, for 70% CL

     and for 90% CL. When adding up the contingency for the total
project which of these CL's were used?

5) A possible one year slippage of the overall ATLAS upgrade schedule
was mentioned as a possibility.

     This might cause a standing army cost increase. Even though the US
responsibility is defined as

     delivery of subsystems, and thus insensitive to standing army
costs, a delayed overall schedule

     might delay the completion of US deliverables due to delays of
prerequisite parts from overseas

    collaborators. How has this possibility taken into account in the
contingency estimation?

6) The HTT project builds on FTK is key ways.   Please reflect on the
aspects of FTK that were

     successful and aspects that were less than successful.   Which
lessons are appropriate to HTT?

     How will these lessons help you manage risk to cost and schedule in
HTT?

7) The key to the proposed change management plan is the CCB.  Please
explain how this committee

     functions, e.g., by consensus, majority vote, unanimity?  How are
conflicts of interest among

     its members managed/mitigated?

8) The core management team has used the US-ATLAS Phase-1 upgrade
project cost and scheduling

     data to inform your expectations for the MREFC HL-LHC project.  
Could you make available to

     us any documentation you have on “lessons learned in Phase 1”?

Part B

9) Provide a pointer to NSF project milestones that are linked to
international milestones

      and indicate how this is tracked in the RLS.

10) Top level talks emphasized the difficulty of controlling the risks
of international

      contributions to the US project. We would like to a specific list
of those contributions,

      if any, and the plans for mitigating these risks (where
possible).  Integration aspects such

      as power, cooling, space (rack and cable), and common projects
such as lpGBT or bPOL are

      of particular interest.

Muon (+Trigger)

11) Point 5j in the NSF charge reads "Performance verification and
acceptance test policies for

     all deliverables are defined and complete. Documentation describes
how acceptance tests will

     verify that deliverables meet design performance specifications and
safety requirements.

      i. QA plans and activities are integrated into the RLS.

     ii. QA and radiation exposure policies are applied consistently
across the project."

     Can you tell us what the status of this documentation is and point
us to it? In particular is the

     SMDT integrated in RLS (this question applies to both trigger and
muon).

12) In the “NSF review tracking_2017 v7” excel spreadsheet, there many
cells which indicate

      the response is “underway” or recommendation status is “in
progress”. Indicate

      which of these have been completed and which are still in progress.

LAr questions:

13) It seemed from the plots showing performance of the ADC in terms of
energy resolution,

      the ultimate goals  were not met for the latest, v2, prototype.
Please be more

      specific on the progress of the ASIC development and what known
issues were addressed

      between v1 and v2 and what issues, so far, need to be addressed in
a v3. As homework,

      can you tell us what improvements to the performance, either in
hardware, software, or

      firmware can  we expect with the current v2 chip before the FDR?

14) Can you be a little more specific on your concerns of the  rad
hardness of the

      Amplifier shaper? Given what is known about radiation damage in
similar circuits,

      what are the potential impacts of what is known/unknown about
potential radiation

      damage to this external (DOE) circuit on the NSF part of the project?

15) The improvement to the Higgs>gamma gamma mass resolution seems an
important benchmark.

      It was unclear from the presentations whether it was just an
impact on the trigger

      or if it affects the offline resolution.  It is also not clear
what algorithm for

      digital filtering was used, and how that corresponds to the
currently envisioned

      algorithm, and what portion of the improvement comes purely from
the dual gain ADC.

      Can you clarify?

16) Can you clarify how the calibration of the gain of the “4x” part of
the ADC relative

      to the “1x” part will be done?  What is the needed accuracy on
this calibration?

17) While measurements of the two-channel coherent noise made using the
LAr Analog

      Testboard meets specifications, what confidence do you have that
the fully

      populated board will also meet the coherent noise specifications? 
What is

      the remediation plan if the coherent noise level is too high?

18) In the interest of high visibility, how well is the US contribution
to the

      LpGPT working. Is the jitter measurement enough to demonstrate
that the US

      contribution is solid?

19) Have any tests of the performance of the off-the-shelf ADC that will be

      used if the 65nm fails been done?  If so, can you describe these
tests?

      What are the considerations that go into deciding whether or not
to prototype

      at FEB2 with this chip?  Has it been radiation tested?

Tile Calorimeter

20) In your documentation, you describe simplifications of the Tile
ELMB2 motherboard.

      Can you explain what allowed this simplification and if it has any
impact

      on the performance of the circuits?

21) What is the magnetic field at that location in ATLAS?  Have the
components been

      tested in that field?

22) How will the experiment pilot inform the production?  Does the
production start

      before that pilot program sees beam?

23) Does the long board get extensive temperature cycling?  Are their
hidden vias?

24) Are there really fuses in the low voltage power supply?

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--

---------------
Tim Andeen
Assistant Professor, Department of Physics
College of Natural Sciences
The University of Texas at Austin
Austin, TX 78712-1192
web: tandeen.web.cern.ch
office (TX): PMA 10.208
office (CERN): 304/1-024
ph (TX):  +1 512 475-9575
ph (CERN): +41 (0)22 76 758 14
email: tandeen AT utexas.edu
---------------