ePIC pfRICH electronics mailing list

["Kiselev, Alexander" <ayk AT bnl.gov>]

  Dear All,

  I'm going to order a dummy passive analog of our future HGCROC3 HRPPD board, see the pre-final drawings here:

https://www.dropbox.com/scl/fi/jwin066f3kmb292t5hyqa/Y05e.zip?rlkey=emgm8ub35zh8h1lx68ck0iuqj&dl=0

https://www.dropbox.com/scl/fi/8djrh47fr1j7tj3yxzowi/Y05e.stp?rlkey=oe9myi35oamaclgw8zfd8cxxy&dl=0

It will be equipped with Samtec ERF8-020-05.0-L-DV-K-TR connectors, which seem to better match a 2mm pad pitch on the HRPPD anode plate than the ERF5 ones. Individual 64-channel spots on this board will later be interfaced to MMCX using respective ERM8 connectors, and provide basic means to connect the new HRPPDs to the existing DRS4 electronics while we are building the ASIC backplane.

  This essentially freezes the mechanical and electrical interface between HRPPDs and the ASIC board as well. Alexey already ordered a ceramic mask to braze (glue) the mounting screws onto the HRPPD anode side, which matches this layout. Be aware that a suggested realistic stay clear area around the 3.8mm and 4.0mm diameter mechanical holes on the top side of ASIC PCB is 7.0mm in this iteration, which is perhaps a bit more than anticipated before. Pierrick, please confirm it is ok. Nothing else changed recently in hole locations, pad pattern, etc.

  Once we are all back from vacations in the first half of September, I suggest that Gabor, with the feedback from Pierrick, Daniel, AK and other colleagues quickly finalizes the document he drafted recently, which would define the mechanical and electrical interface between ASIC and FPGA boards, as well as with the cooling layout, at which point these design efforts can effectively proceed in parallel. Let me know whether there are other suggestions.

  Best regards,

    Alexander.

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