ePIC pfRICH electronics mailing list

["Cacace, Daniel" <dcacace AT bnl.gov>]

Hi Alexander,

I’m booked Thursday morning, but should be available all afternoon. 

-Dan

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From: Eic-projdet-pfrich-electronics-l <eic-projdet-pfrich-electronics-l-bounces AT lists.bnl.gov> on behalf of Kiselev, Alexander via Eic-projdet-pfrich-electronics-l <eic-projdet-pfrich-electronics-l AT lists.bnl.gov>
Sent: Wednesday, November 8, 2023 11:53:53 AM
To: Camarda, Timothy via Eic-projdet-pfrich-electronics-l <eic-projdet-pfrich-electronics-l AT lists.bnl.gov>
Subject: [Eic-projdet-pfrich-electronics-l] V0 (pre)final design meeting on Friday

 

  Dear All,

  (addressing the whole list)

  Given the doodle poll outcome, it looks like we are again pretty much out of sync with each other. 

  The proposal then is to schedule this meeting to Friday 9am EST (15:00 CET), when both Pierrick (for an hour) and Gabor can make it, and reserve up to 2h time slot, assuming Miklos can join at 10am EST with Gabor still available:

https://bnl.zoomgov.com/j/1619779791?pwd=TUtVak9TMjdsb05CbkVrZmh2a2JzZz09

  Norbert seems to be out of luck this time. Also, it is a holiday in the US.

  Daniel, Tim, are you around for a chat in person on Thursday?

  Gabor, Pierrick: please send me the actual current ASIC and FMC board drawings some time tomorrow Thursday to post them on dropbox. I will send out an update of the interface document shortly afterwards.

  I'm not sure we are in a production-ready state after this meeting, but let's make an effort to be as close to the V0 freeze beginning next week as possible.

  Cheers,

    Alexander.