ePIC pfRICH electronics mailing list

[nagy g <hunagabo AT gmail.com>]

Hi Alexander,

I did not want to mess up your dropbox structure, so instead I am sending a link to the new (hopefully final) version of the passive board and the requested updates for the specification document.

First, the pin assignment of the ERF5 conector can be found here in a FMC_HPC_J22_004.xlsx:

https://docs.google.com/spreadsheets/d/1PM8OqKC-0VQgOPjQjBHTgi2sJubNKc2s/edit?usp=drive_link&ouid=113700172830584138501&rtpof=true&sd=true

It also includes the HPC connector and FPGA pin assignment just in case...

Updated the silk layer with the BNL/ORNL/Omega and DEIK logos what I could find on the web. If someone need a different one please send that to me.

(Debrecen University logo is quite difficult, so I could not include that...)

And finally, the current output package can be found here: https://drive.google.com/file/d/1tfJ5WGjsKwhA9P40UuEbSTPFSsG3gB5l/view?usp=drive_link

It also includes a new picture about the current passive board with on the current ASICs board.)

Best Regads, gabor

Kiselev, Alexander via Eic-projdet-pfrich-electronics-l <eic-projdet-pfrich-electronics-l AT lists.bnl.gov> ezt írta (időpont: 2023. nov. 11., Szo, 13:59):

  Hello colleagues,

  based on the "V0 design freeze" meeting yesterday, and earlier discussions, the immediate plans to finalize the PCB design and start productions are:

  Mon Nov,13 -> FMC board design sent out (to this mailing list?) for final comments

  Mon Nov,13 -> ASIC board STEP file is distributed 

  Wed Nov,15 -> FMC board production launch

  Fri     Nov,17 -> ASIC board design sent out for final comments

  Tue   Nov,21 -> ASIC board production launch

  Fri     Dec,  1  -> FPGA board design sent out for final comments [hopefully earlier!]

  Tue   Dec,  5  -> FPGA board production is launched [hopefully earlier!]

  "Production launch" means asking for a final manufacturer quote if needed and placing a PO.

Then it takes whatever it takes.

  Late finish of the FPGA board should not be a real problem, because it will be functionally equivalent to a [FMC board + twinax cable + KCU105 kit] set with the same FPGA and interfaces.

  Cooling system design will hopefully be also finalized on a time scale of two weeks.

  Cheers,

    Alexander.

 

--
Eic-projdet-pfrich-electronics-l mailing list
Eic-projdet-pfrich-electronics-l AT lists.bnl.gov
https://lists.bnl.gov/mailman/listinfo/eic-projdet-pfrich-electronics-l