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  • From: "Kiselev, Alexander" <ayk AT bnl.gov>
  • To: "Camarda, Timothy via Eic-projdet-pfrich-electronics-l" <eic-projdet-pfrich-electronics-l AT lists.bnl.gov>
  • Subject: [Eic-projdet-pfrich-electronics-l] Immediate plans for V0 implementation
  • Date: Sat, 11 Nov 2023 12:59:13 +0000

  Hello colleagues,

  based on the "V0 design freeze" meeting yesterday, and earlier discussions, the immediate plans to finalize the PCB design and start productions are:

  Mon Nov,13 -> FMC board design sent out (to this mailing list?) for final comments

  Mon Nov,13 -> ASIC board STEP file is distributed 

  Wed Nov,15 -> FMC board production launch

  Fri     Nov,17 -> ASIC board design sent out for final comments

  Tue   Nov,21 -> ASIC board production launch

  Fri     Dec,  1  -> FPGA board design sent out for final comments [hopefully earlier!]

  Tue   Dec,  5  -> FPGA board production is launched [hopefully earlier!]

  "Production launch" means asking for a final manufacturer quote if needed and placing a PO.
Then it takes whatever it takes.

  Late finish of the FPGA board should not be a real problem, because it will be functionally equivalent to a [FMC board + twinax cable + KCU105 kit] set with the same FPGA and interfaces.

  Cooling system design will hopefully be also finalized on a time scale of two weeks.

  Cheers,
    Alexander.

 



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