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["Pat Bailey" <patrick.bailey AT palpilot.com>]

Hi Gabor,

 

You can use metric and 100um/250um is fine.

 

Thank you.

 

Regards,

 

Pat Bailey

Senior Field Application Engineer

 

Tel: 507 640-0339

patrick.bailey AT palpilot.com

www.palpilot.com

 

 

From: nagy g <hunagabo AT gmail.com>
Sent: Wednesday, November 29, 2023 2:08 PM
To: Pat Bailey <patrick.bailey AT palpilot.com>
Cc: Fred.Pascucci AT palpilot.com; Cindy.ho AT palpilot.com; vicky.sun AT palpilot.com.cn; Camarda, Timothy via Eic-projdet-pfrich-electronics-l <eic-projdet-pfrich-electronics-l AT lists.bnl.gov>; Alexander <ayk AT bnl.gov>; Timothy <tcamarda AT bnl.gov>
Subject: Re: HRPPD_FPGA_BOARD_V0

 

Thank you Pat! I changed the L5 to 0.5oz, which was a mistake.

 

Yes, the overal thickness is palned to be ~62mil on this board too.

 

I do design in mm and 4/10mil for laser vis can be 100um/250um, or should be axactly 4/10mil? (just to make sure after conversion it will not cause an error...)

 

Thanks, gabor

 

 

Pat Bailey <patrick.bailey AT palpilot.com> ezt írta (időpont: 2023. nov. 29., Sze, 17:03):

Hi Nagy,

 

The structure you noted would be built as stacked copper filled laser vias L1-L2, L2-L3, L6-L7, L7-L8, mechanical drilled vias L3-L6, and through vias L1-L8 is ok.  The laser vias should be 4mil with 10mil pads.

 

Are you looking for the same ~62mil overall board thickness?  I noted in your stackup diagram that L5 is 1oz.  It should be 0.5oz or L4 should also be 1oz to keep the stackup symmetrical.

 

Thank you.

 

Regards,

 

Pat Bailey

Senior Field Application Engineer

 

Tel: 507 640-0339

patrick.bailey AT palpilot.com

www.palpilot.com

 

 

From: nagy g <hunagabo AT gmail.com>
Sent: Wednesday, November 29, 2023 1:22 AM
To: Patrick Bailey <patrick.bailey AT palpilot.com>; Fred.Pascucci AT palpilot.com; Cindy.ho AT palpilot.com; vicky.sun AT palpilot.com.cn; Camarda, Timothy via Eic-projdet-pfrich-electronics-l <eic-projdet-pfrich-electronics-l AT lists.bnl.gov>; Alexander <ayk AT bnl.gov>; Timothy <tcamarda AT bnl.gov>
Subject: HRPPD_FPGA_BOARD_V0

 

Hello Fred, Pat, Cyndy and Vicky,

 

I am working on the nex board in Alexander's project, and would like to get some help in advanced. Just to avoid as much as possible, design chages after routing.

 

This board is similar in size and shape to the previous one, but more dense in booth side. So probably 8 layer is needed and has a lot of components pad conflicting with the opposit side component.

 

Current plan is to use a HDI 2-4-2 structure (micro VIA 1-2, 1-3, 6-8,7-8 and burried VIA 3-6).

First question would be the stackup. Could you advice what stackup I should use? (need 50Ohm impedance on 1,3,6,7)

 

I put together something like this (using IT180A):

 

The next questions would be the uVIA usage.

- Can I use stacked VIAs or staggered VIA is prefered?

- skip VIA is suported or should I avoid? (L1-L3 and L6-L8)

- how much uVIA and through hole VIA can be mixed on same board? (it is recommended to do not mix them in same design in FPGA datasheet, but I have no experience in this.. But would be beneficial to use TH VIA for power supplies.)

 

This is all for first iteration :)

 

Thanks, gabor