sPHENIX MAPS tracker discussion

[John Haggerty <haggerty AT bnl.gov>]

-------- Forwarded Message --------
Subject:        Instrumentation Division Seminar Next Week
Date:   Thu, 14 Sep 2017 14:42:10 +0000
From:   Warren, John B <warren AT bnl.gov>





*Instrumentation Division Seminar*

*Wednesday, September 20, 2017*

*Title:*             Common Readout Card (CRU) for the ALICE Run3 Upgrade

*Speaker:*       Jozsef Imrek, CERN

*Time:*2:30 p.m.

*Place:*          Large Conference Room, BLDG 535B (Instrumentation 
Division)

*Abstract:*****

**

******

ALICE is preparing a major upgrade for 2021.

All subdetectors upgrading their counting room DAQ electronics will use 
a common hardware to receive physics data: the Common Readout Unit 
(CRU). The CRU is a PC based readout card featuring an Intel Arria 10 
FPGA, up to 48 full duplex optical links with a maximum line rate of 10 
Gbit/s, and a Gen3 x16 PCIe interface for host connectivity.

The same CRU will also distribute the LHC clock and trigger 
synchronously to most of the upgrading subdetectors (to ~7800 front end 
cards).

Details of the CRU readout card, its usage in ALICE, and the current 
status and future plans for hardware production, FPGA firmware, and 
readout software will be presented.


--
John Haggerty
email: haggerty AT bnl.gov
cell: 631 741 3358