sphenix-maps-l AT lists.bnl.gov
Subject: sPHENIX MAPS tracker discussion
List archive
- From: Martin Purschke <purschke AT bnl.gov>
- To: Ming Liu <ming AT bnl.gov>, sphenix-mvtx-l <sphenix-maps-l AT lists.bnl.gov>, "Mead, Joseph" <mead AT bnl.gov>, John Kuczewski <jkuczewski AT bnl.gov>
- Subject: Re: [Sphenix-maps-l] FW: sPHENIX GTM bit pattern
- Date: Thu, 1 Oct 2020 20:31:23 -0400
All,
what Cameron shows on his slide 2 (and the left column) is right. The
strain of FELIX firmware where the code snippet you show comes from
pre-dates that slight adjustment (which are documented in the TDR, too,
pg 172). John and I have yet to sit together and get that implemented on
the older Felix systems - we haven't been using the newest GTM firmware
in order not to change something in the middle of the almost permanent
state of deadline pressure before we went to the home office.
Just today Joe and I had some back and forth about some minor bug fixes
in the now combined GL1+GTM firmware and support software that I'm
currently testing in 1008 and that will be the new gold standard (new
firmware, new better Linux system, etc etc). Please be patient for a few
more days.
Best,
Martin
On 10/1/20 16:09, Ming Liu wrote:
> FYI,
>
> Resend bounced email from Cameron about MVTX/sPHENIX GTM bit pattern.
>
>
>
> Cameron – I added your BNL email to the mvtx mailing list.
>
>
>
> Ming
>
>
>
> --
>
> Ming Xiong Liu
>
> P-25, MS H846 TEL: 505-667-7125
>
> Physics Division 631-344-7821(BNL)
>
> LANL 630-840-5708(FNAL)
>
> Los Alamos, NM 87545 FAX: 505-665-7020
>
>
>
>
>
> *From: *"Dean, Cameron" <cdean AT bnl.gov>
> *Date: *Thursday, October 1, 2020 at 11:42 AM
> *To: *"Mead, Joseph" <mead AT bnl.gov>
> *Cc: *sPHENIX-MAPS-l <sphenix-maps-l-bounces AT lists.bnl.gov>
> *Subject: *sPHENIX GTM bit pattern
>
>
>
> Hi Joe,
>
> The MVTX firmware team has been looking at the interface between the
> FELIX card and the GTM. We noticed that there is a mismatch between the
> bit pattern we found in the GTM documents and what is decoded in FELIX.
> Would it be possible to confirm what the 16-bit pattern sent for each
> GTM clock is?
>
> I’ve attached some slides explaining this in a little more detail but,
> on our side, I see that the ‘End Data’ and ‘Mode Enable’ bits are in a
> different order.
>
>
> Cheers,
> Cameron
>
> P.S. The comparison of bits we see is:
>
>
>
> *Bits from GTM*
>
>
>
> *Bits set in FELIX*
>
> Mode bits / BCO
>
>
>
> 0-7
>
>
>
> 0-7
>
> Beam Clock
>
>
>
> 8
>
>
>
> 8
>
> LVL1 Accept
>
>
>
> 9
>
>
>
> 9
>
> End Data
>
>
>
> 10-11
>
>
>
> 11-12
>
> Mode Bit Enable
>
>
>
> 12
>
>
>
> 10
>
> User Bits
>
>
>
> 13-15
>
>
>
> 13-15
>
>
>
>
> _______________________________________________
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> sPHENIX-MAPS-l AT lists.bnl.gov
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>
--
Martin L. Purschke, Ph.D. ; purschke AT bnl.gov
; http://www.phenix.bnl.gov/~purschke
;
Brookhaven National Laboratory ; phone: +1-631-344-5244
Physics Department Bldg 510 C ; fax: +1-631-344-3253
Upton, NY 11973-5000 ; skype: mpurschke
-----------------------------------------------------------------------
-
[Sphenix-maps-l] FW: sPHENIX GTM bit pattern,
Ming Liu, 10/01/2020
-
Re: [Sphenix-maps-l] FW: sPHENIX GTM bit pattern,
Martin Purschke, 10/01/2020
- Re: [Sphenix-maps-l] FW: sPHENIX GTM bit pattern, Ming Liu, 10/02/2020
-
Re: [Sphenix-maps-l] FW: sPHENIX GTM bit pattern,
Martin Purschke, 10/01/2020
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