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Subject: sPHENIX MAPS tracker discussion

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  • From: Martin Purschke <purschke AT bnl.gov>
  • To: Jakub Kvapil <jakub.kvapil AT cern.ch>, "sPHENIX-trigger-l AT lists.bnl.gov" <sPHENIX-trigger-l AT lists.bnl.gov>, "sphenix-maps-l AT lists.bnl.gov" <sphenix-maps-l AT lists.bnl.gov>
  • Subject: Re: [Sphenix-maps-l] Slides for TWEPP conference
  • Date: Mon, 25 Sep 2023 21:26:07 -0400

Hi Jakub

interesting slides.

Some comments -

Slide 4:

sPHENIX is definitely higher than 3m...

RHIC has an ~60MHz clock, 56.299 to be exact, and 1/6 of that is the bunch crossing rate. (and yes for the MVTX we provide a 40MHz clock so it feels like at the LHC)

I would leave out the "due to calorimeter limit", 15KHz was the design

The "MVTX and INTT" with the sub-point "Tracking Detectors capable of streamed readout" makes it sound like only those 2 can do it. Not true.
BTW, I always see it called streaming readout - small point.


The annotations you added that label the groups with oHCal/iHCal etc on Slide 9 make it look like overall there are just 6 such PCs. You have to get across that this is only a schematic overview.

Again, I know you are using MVTX and INTT, but the TPC is also SRO-capable.

Slide 10 - the thing with the local mode is kinda irrelevant in this context.

Not sure what to make of the sentence about the busy - it's misleading. The GL1 maintains a global busy that the GTMs feed into.

You mangled and re-drew the right lower diagram from my slides but made it wrong. There are 4 LL1 fibers coming in, you draw 6 and say "56". (And it's 4 Lemos, not 8.) I find what I have in several of my presentations (I showed you the shift training slides) that explains what constitutes a "Granule" better and clearer.

Slide 11 -

"stretch the latency down" seems like an odd choice of words.

point 2) JH can correct me, I believe we have 158m trunks + whatever the patches add, and they are fibers, not cables.

On Sl 14, with "extract the Wupper module", do you mean remove? How will you configure the unit then w/o PCIe access? (Just curious).

Ok, have fun in Italy!

Martin


On 9/25/23 19:10, Jakub Kvapil wrote:
Dear all,

some of you get know during the QM that we have a small R&D project for developing FPGA based ML triggering system which demonstrator we plan to > deploy for the pp run at sPHENIX.
When I was preparing slides, it become obvious that without introducing the sPHENIX DAQ and triggering system in more detailed manner, the overall talk will not make much sense.
Thus, we have decided to circulate the slides also within sPHENIX.

Any comments and questions are highly appreciated. I will update the coloring to be more uniform later.
They are for the TWEPP conference - Topical Workshop on electronics for particle physics (https://indico.cern.ch/event/1255624/ <https://indico.cern.ch/event/1255624/>), thus heavily specialized. The time is 16+4.
Please provide any comments by this Wednesday, as I am flying on Friday (sorry for later notice)

Thanks a lot
Best regards
Jakub



--
Martin L. Purschke, Ph.D. ; purschke AT bnl.gov
; http://www.phenix.bnl.gov/~purschke
;
Brookhaven National Laboratory ; phone: +1-631-344-5244
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