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[Thomas K Hemmick <tkhemmick AT gmail.com>]

Hi guys

I agree with Ivan about the favorite and I note that the plan shown on slide 8 allows us to try this and all other variations.  It looks like a good plan to me. 

Tom

On Tue, Dec 17, 2019 at 3:51 PM Sakaguchi, Takao <takao AT bnl.gov> wrote:

Hi Ivan,

Thanks for your input!

Takao


On 12/17/2019 3:43 PM, Kotov, Ivan wrote:
> Hi Takao,
>
> I would vote for modified ATLAS scheme, slide 5.
> The protection is most effective when it is directly connected to the pad and ~ 1pF capacitance increase looks like a reasonable price to pay considering  12-33 pF pad cap (slide 3).
>
> my 2 cents,
> Ivan
>
> On 12/17/19, 14:26, "Sphenix-tpc-l on behalf of Sakaguchi, Takao"<sphenix-tpc-l-bounces AT lists.bnl.gov on behalf of takao AT bnl.gov>  wrote:
>
>      Dear All,
>
>        I sat down with Vinnie from ATLAS, got some input from
>      several others, and came up with a set of input protection
>      schemes that we may want to implement in the next
>      version of the FEE board and test. See the slides attached.
>
>        Vinnie said that the most upstream (detector side)
>      resistors had more chance of being damaged compared
>      to the downstream, which is reasonable.
>
>        I would like to hear your input, hopefully by the end of
>      this week. If no input, I would like to go with the proposed
>      scheme shown on the slide 8, which has maximum degree
>      of freedom for testing as far as I can tell.
>
>      Takao
>
>
>
>

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