Star-fst-l mailing list

[Gerard Visser <gvisser AT indiana.edu>]

Yes, I'll look at that quickly. It seems reasonable to build the v3 T-board, 
certainly so if we need many for effective testing. The most critical thing as I 
see it is to prove (with data) the latest hybrid designs and the sensors are 
ready for production or not. Sorry that I could not make this morning's meeting.

        Gerard

On 12/5/2019 6:48 PM, Aschenauer Elke-Caroline wrote:
> Dear Zhenyu,
>
> I sent an email already yesterday where I made clear I would go to v3 
> immediately.
> So lets do this. Gerard can you please review the changes if not yet done, so we 
> can proceed.
>
> Cheers elke
>
>
> > On Dec 5, 2019, at 17:16, Zhenyu Ye <yezhenyu2003 AT gmail.com 
> > <mailto:yezhenyu2003 AT gmail.com>> wrote:
> >
> > Hi Elke, Gerard,
> >
> > At the FST meeting today, we discussed whether or not to make v3 T-boards or 
> > stay with v2.1 T-boards with modifications. The former will cost $2093 for 10 
> > boards, with a 10-day delivery time. We also discussed the options for making 
> > the cables for prototype module testing, using the old test cables or the new 
> > purple cables. The former will cost $1350 (to solder cables onto the T-board), 
> > and the latter will cost ~$3700 (to solder cables onto the T-board, and the 
> > connectors on the other ends).
> >
> > (Some cost numbers in the message above may not be very accurate, but should 
> > be very close to what Mike said at the meeting).
> >
> > If the extra cost for BNL is not an issue, using v3 T-board and new purple 
> > cables is the preferred option. It should also meet the requirement of getting 
> > cables ready by the end of January 2020, if the order of the v3 T-boards goes 
> > out this week or beginning of next week. The latter will need Gerard’s review 
> > and sign-off of v3 T-board layout sent by Jianing:
> >
> >
> > > On Dec 4, 2019, at 3:52 AM, 董家宁 <jndong AT sdu.edu.cn 
> > > <mailto:jndong AT sdu.edu.cn>> wrote:
> > >
> > > Hi Gerard,
> > > I just finished the layout for v3.0 T-board, please find the gerber files in 
> > > the attachment or the following link. 
> > > (https://drupal.star.bnl.gov/STAR/blog/jndong/191204-gerber-files-t-board-v30)
> > > Since the new year is approaching, I think it will take at least 4~5 weeks 
> > > for production in China after your final approval.
> > >
> > > Best,
> > > Jianing
> >
> > Please let us know if you have any question/comment.
> >
> > Zhenyu
> >
> > > On Dec 4, 2019, at 10:36 AM, Gerard Visser <gvisser AT indiana.edu 
> > > <mailto:gvisser AT indiana.edu>> wrote:
> > >
> > > hi Mike,
> > > I _finally_ -- sorry for huge delays! -- had a careful look at the list of 
> > > modifications to implement T-board 3.0 functionality on the existing 2.1 
> > > boards, for first tests.
> > > You don't have to remove R41 or U9, they can stay. But OK to remove 
> > > either/both.
> > > You don't have to remove R15 and R17, they can stay. But OK to remove them. 
> > > They are in parallel with R37 and R39, and the effective value 5 Ohms is no 
> > > doubt just as good as 10 Ohms.
> > > Overall, keep in mind the removed items could be from "b" group or from "a" 
> > > group and whichever may be easier because of placement details is fine. I 
> > > noticed you elected a mixture (reset and TMP102 from "a", SDA/SCL termination 
> > > from "b", it's fine).
> > > To MATCH the 3.0 schematic, we ALSO must remove R32, R33, R34, R35 and wire 
> > > jumpers (small and neat as we can) from net TRGa_P to net TRGb_P, and so on. 
> > > 4 jumpers.
> > > We must ALSO wire jumpers (not needing to be that small and neat as the TRG & 
> > > CLK ones!) from net SDAa_in to net SDAb_in and from net SCLKa_in to SCLKb_in.
> > > We must ALSO remove F3 and F4.
> > > And I am presuming here that the power nets GNDa and GNDb are really one net, 
> > > and VDDa and VDDb, and VSSa and VSSb, and specifically I mean that they are 
> > > reasonable on the layout (low impedance power connections between all points 
> > > on these nets). Have you looked into that? If you could please that would be 
> > > great. I hope it is so.
> > > I attach here my markup of the 2.1 schematic corresponding to my comments 
> > > above (and your plan below). If the power planes are good for it then doing 
> > > the marked changes should take care of it, I think. (Please check my work too.)
> > >
> > > On the separate matter of whether to just build 3.0 vs. to hack 2.1 to it, 
> > > let's hear your about your quotes/leadtime options. If we need four units for 
> > > first tests, and it seems like that will just be a lot easier or if you're 
> > > unsure about whether these hacks to v2.1 will really work out (in terms of 
> > > matching 3.0 effectively, or in terms of effort required), it may be better 
> > > to do that.
> > > I hope we will not have to be making further changes based on fit or 
> > > performance after the first real prototypes are assembled. That's the 
> > > motivation to get what we can out of 2.1 (if practical) so that 3.0 can be 
> > > more definitely the last version. But it may be best to just move on 3.0 and 
> > > hope for the best, anyway the T-board is a small matter compared to the 
> > > hybrids. Hopefully we are at the last version on those but the tests will 
> > > have to prove it.
> > > Sincerely,
> > >
> > > Gerard
> > >
> > >
> > >
> > > On 11/14/2019 4:41 PM, Capotosto, Michael wrote:
> > > > Gerard,
> > > > Have you had a chance yet to review these T-Board V2.1 mods?
> > > > --Mike
> > > > -----Original Message-----
> > > > From: Capotosto, Michael
> > > > Sent: Tuesday, November 12, 2019 9:11 AM
> > > > To: '董家宁' <jndong AT sdu.edu.cn <mailto:jndong AT sdu.edu.cn>>; 'gerard visser' 
> > > > <gvisser AT indiana.edu <mailto:gvisser AT indiana.edu>>
> > > > Cc: 'zhenyu ye' <yezhenyu2003 AT gmail.com <mailto:yezhenyu2003 AT gmail.com>>
> > > > Subject: RE: Re: [Star-fst-l] Weekly FST meeting - 10/24/2019
> > > > Hey Gerard,
> > > > Just following up regarding these T-Board modifications, we still need to do 
> > > > the mods before we give the t-boards to the vendor, please look this over 
> > > > and let me know.
> > > > --Mike
> > > > -----Original Message-----
> > > > From: Capotosto, Michael
> > > > Sent: Wednesday, October 30, 2019 1:02 PM
> > > > To: 董家宁 <jndong AT sdu.edu.cn <mailto:jndong AT sdu.edu.cn>>; gerard visser 
> > > > <gvisser AT indiana.edu <mailto:gvisser AT indiana.edu>>
> > > > Cc: zhenyu ye <yezhenyu2003 AT gmail.com <mailto:yezhenyu2003 AT gmail.com>>
> > > > Subject: RE: Re: [Star-fst-l] Weekly FST meeting - 10/24/2019
> > > > Gerard,
> > > > If the new T-Board V3 schematic is all good, I don't think it's necessary to 
> > > > cut any traces to "replicate" the V3 board using the V2.1 board.
> > > > **All designators below refer to V2.1 Schematic**
> > > > For the double resets: Remove: U9, U10, R41, R42, R45.
> > > > For the double temp sensors: Remove U8.
> > > > For the bus terminations: Remove R14-17.
> > > > Please let us know soon, as we must make these modifications before we hand 
> > > > the boards back over to the vendor, I'd like to leave him enough time to 
> > > > complete this before the December deadline.
> > > > Thanks,
> > > > Mike
> > > > -----Original Message-----
> > > > From: 董家宁 <jndong AT sdu.edu.cn <mailto:jndong AT sdu.edu.cn>>
> > > > Sent: Tuesday, October 29, 2019 9:49 PM
> > > > To: gerard visser <gvisser AT indiana.edu <mailto:gvisser AT indiana.edu>>
> > > > Cc: Capotosto, Michael <capotosto AT bnl.gov <mailto:capotosto AT bnl.gov>>; 
> > > > zhenyu ye <yezhenyu2003 AT gmail.com <mailto:yezhenyu2003 AT gmail.com>>
> > > > Subject: Re: Re: [Star-fst-l] Weekly FST meeting - 10/24/2019
> > > > Hi Mike and Gerard,
> > > >  Thank you very much for pointing out the error.
> > > >  The address pin on outer hybrid does need to be connected to the SCK pin 
> > > > (U1->PIN1).
> > > >  Please let me know if you find any other mistakes.
> > > >  Thanks!
> > > > Best,
> > > > Jianing
> > > > > -----原始邮件-----
> > > > > 发件人: "Gerard Visser" <gvisser AT indiana.edu <mailto:gvisser AT indiana.edu>>
> > > > > 发送时间: 2019-10-30 00:38:38 (星期三)
> > > > > 收件人: "Capotosto, Michael" <capotosto AT bnl.gov 
> > > > > <mailto:capotosto AT bnl.gov>>, "董家宁"
> > > > > <jndong AT sdu.edu.cn <mailto:jndong AT sdu.edu.cn>>
> > > > > 抄送: "zhenyu ye" <yezhenyu2003 AT gmail.com <mailto:yezhenyu2003 AT gmail.com>>
> > > > > 主题: Re: [Star-fst-l] Weekly FST meeting - 10/24/2019
> > > > >
> > > > > hi Mike,
> > > > > Thanks for the careful looks - I need to look over things still but
> > > > > will do. It sounds like some issues remain maybe.
> > > > > The APV chips are on the same I2C bus, that is the main thing. And I
> > > > > think you're right that the ALERT pin is only used on the T-board,
> > > > > this implements the overtemperature interlock. But this traces to
> > > > > historical things of the way it was first implemented (for the FGT)
> > > > > and I think I have to go read some old emails to remember why we made the 
> > > > > choices we did for IST.
> > > > >
> > > > > Gerard
> > > > >
> > > > >
> > > > > On 10/29/2019 12:29 PM, Capotosto, Michael wrote:
> > > > > > Jianing,
> > > > > >
> > > > > > Thanks for the review.
> > > > > >
> > > > > > Jianing and Gerard,
> > > > > >
> > > > > > Regarding the hybrids and T-Board, I’ve got a few questions.
> > > > > >
> > > > > > 1. There are TMP102 temperature sensors on the inner hybrid, outer hybrid,
> > > > > >    T-Board, and Patch Panel Board, all tied to the same I2C line. See 
> > > > > > attached.
> > > > > >     1. PPB has address tied to SDA
> > > > > >     2. T-Board V3.0 has it tied to VSS
> > > > > >     3. Inner Hybrid tied to V+/VDDa
> > > > > >     4. ***Outer Hybrid tied to Ground*** I believe this is an error…Ground and
> > > > > >        VSS are separated, and only AC coupled on the T-Board. I think you
> > > > > >        intended to tie this pin to VSS – the same as the “GND pin” pin 2 
> > > > > > of the
> > > > > >        TMP102 – is this the case? If so, there is still a conflict between the
> > > > > >        T-Board V3.0 address and the outer hybrid address! We should tie 
> > > > > > this to
> > > > > >        SCL, according to the Datasheet to get our fourth address 
> > > > > > (0b1001011, 0x4B)
> > > > > >     5. /ALERT Pins
> > > > > >
> > > > > > i.These are open drain pins, it appears on the patch panel the pin
> > > > > > was left floating. Are there
> > > > > > advantages/disadvantages/recommendations for floating vs pull up vs pull down?
> > > > > >
> > > > > > ii.The T-Board uses the ALERT output to pull the reset down through
> > > > > > a 20k resistor…I just want to confirm, this functionality isn’t used
> > > > > > directly from either hybrid or the PPB, is this correct/intentional?
> > > > > >
> > > > > > I’m not sure if you guys have a copy of the PPB schematic I have,
> > > > > > I’m not sure where I even got it from, I’ve attached a copy. Gerard,
> > > > > > do you know if there’s any other addressable devices elsewhere on
> > > > > > this particular I2C bus? Perhaps in the MPOD crate/one of the modules this 
> > > > > > ties into/etc.?
> > > > > >
> > > > > > Other than that…nothing else is jumping out at me.
> > > > > >
> > > > > > --Mike
> > > <Tboard_2.1_hack_to_3.0_redlines_GV.pdf>_______________________________________________
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> >
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