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[Gerard Visser <gvisser AT indiana.edu>]

hi Jianing, Zhenyu,
	I looked over the T-board 3.1 (finally - sorry I kept interrupting that). I 
don't see any crucial concerns in this layout. It is worth saying though, as 
mentioned before at the start of this project, that the T board layout would 
have been a lot simpler and better (lower impedance power connections) if done 
as a 6-layer board. This is obviously quite true of the present layout, which 
runs the power connections back and forth across the board in a couple of places 
connected by moderately skinny copper. I think the layout is reasonable as it 
is, and certainly the hybrids involve more and longer such contortions but that 
is unavoidable given that >2 layers there would be much more difficult. I think 
that you have the traces and plane segments on the T board carrying power about 
as good as can be done given the overall 4 layer plan and component locations, I 
think there is nothing that needs to be changed about it.
	I would recommend now either fabricate the remaining quantity, or if it is 
possible make a test (in UIC setup) with one of the ones from the early 
fabrication that was done and be sure that performance is about the same as 
before. (High rate pedestal test is probably the best test.) I think if it is 
feasible (when are those first boards available?) a test before fabricating the 
rest of them is always good - but I don't think there is any particular worry here.
        Sincerely,

                Gerard


p.s. I did not check any dimensions, I assume you have done that thoroughly.