U.S. ATLAS HL-LHC Upgrade LAr Level 2 and Level 3 Managers Mailing List

[John Parsons <parsons AT nevis.columbia.edu>]

Hi Hong,

        Thanks for posting a draft of your L3 slides.  I give some comments 
below.

                John

General – your page numbers are somehow messed up and not sequential 
(eg. your last page number is listed on the slide as 47 but you have 
only 35 pages in the pdf!!); in my comments below I list the page number 
shown on that particular slide

p. 2 – remove arrow

p. 10 – “started preparing …”
  - not all lines are same font size; make consistent

p. 11 – capitalize Preproduction in title
        
p. 12 – you say “No I2C errors observed!” but then show a plot showing 
regions with I2C errors??  Rephrase to make it not seemingly contradictory
  - you should also explain what the plot is (eg. explain phase, …)

pp. 13-14 – maybe remind what specs are for these parameters?

p. 15 – you say <1 min, but looks like sum would be a bit more than 1 
min once you test both 25 and 50 Ohm

p. 16 – maybe mention also socket implemented on testboard

p. 18 – mention each ASIC has unique QR code that will be used to put 
results in dB

p. 19 – “place in different “good” and “bad” trays”

p. 20 – explain wafers ordered via “ATLAS priming” process to avoid 
delays (maybe move this slide to later, under Large Procurements”

p. 24 – “… reduced it’s the…”

p. 32 – last bullet is outdated since FDR and preprod are both complete

p. 36 – say pkging delay is due to supply chain
 - stress (again) that not on Critical Path (in fact, once FEB2 delay 
BCP processed you will be even farther off)

p. 39 – move here the earlier text about priming etc.

p. 42 – only list things since CD-2/3; ie. get rid of the really old 
retirements (such as 65 nm)
 - add that BCP115 resulted from French delay in robot development

pp. 42-43 – could shorten and combine?? (do we need pie chart? Maybe put 
in backup)

p. 44 – “yield” (not yields)
  - “QC test of the production chips”

-	Somewhere in talk add something about QC dB work, particularly since 
DOE is paying for Saroj’s time for this.  So we want to stress its 
importance



On 1/27/24 4:10 PM, Ma, Hong wrote:
> Hi all,
>
>                  I uploaded my slides for IPR to the indico.
>                  Comments will be appreciated.
>
>                  Best,
>
>                  Hong.
>
> From: Usatlas-hllhc-lartl2l3-l <usatlas-hllhc-lartl2l3-l-bounces AT lists.bnl.gov> on 
> behalf of John Parsons <parsons AT nevis.columbia.edu>
> Date: Thursday, January 25, 2024 at 6:18 PM
> To: usatlas-hllhc-lartl2l3-l AT lists.bnl.gov 
> <usatlas-hllhc-lartl2l3-l AT lists.bnl.gov>
> Subject: [Usatlas-hllhc-lartl2l3-l] weekly mtg
>
> Hi all,
>
>       We will meet tomorrow at the usual time.  The Indico page is at
> https://indico.bnl.gov/event/22077/.  I will need to leave a bit early,
> so we will try keep the mtg short.
>
>       Regards,
>                   John
> --
> ______________________________________________________________________
>
> John Parsons
> Nevis Labs,              Email: parsons AT nevis.columbia.edu
>    Columbia University   Phone: (914) 591-2820
> P.O. Box 137            Fax: (914) 591-8120
> Irvington, NY 10533     WWW: 
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>
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--
______________________________________________________________________

John Parsons
Nevis Labs,             Email: parsons AT nevis.columbia.edu
 Columbia University    Phone: (914) 591-2820
P.O. Box 137            Fax: (914) 591-8120
Irvington, NY 10533     WWW: 
https://urldefense.com/v3/__http://www.nevis.columbia.edu/*parsons/__;fg!!P4SdNyxKAPE!FNBWWPzjug3rcej9ahSIVfjTLYwO5HkiHiVDymfc-j4FkMCAmuJaLwmi8a6QNQOzMGBE5Y-OL7_Dt5gRAvZ-xAzrtzGD8MjvLzKO4tsNI2GQVg$
      

______________________________________________________________________