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[Eic-projdet-pfrich-electronics-l] HRPPD ASIC backplane milestones

From: "Kiselev, Alexander" <ayk AT bnl.gov>
To: "Camarda, Timothy via Eic-projdet-pfrich-electronics-l" <eic-projdet-pfrich-electronics-l AT lists.bnl.gov>
Subject: [Eic-projdet-pfrich-electronics-l] HRPPD ASIC backplane milestones
Date: Wed, 27 Sep 2023 06:04:00 +0000

Hello colleagues,

If one forgets about names and detailed description of activities, and only thinks in terms of milestones, to start with, then I ended up with the attached schedule.

I'd say, unless the V0 iteration happens to be a very good first shot, the schedule is barely realistic. Please provide your feedback, and I will take another couple of days to produce a more detailed version, separating ASIC / FPGA / cooling / firmware / driver / etc items and adding names.

Cheers,

Alexander.

Attachment: hrppd-asic-interface-schedule.v00.pdf
Description: hrppd-asic-interface-schedule.v00.pdf

[Eic-projdet-pfrich-electronics-l] HRPPD ASIC backplane milestones, Kiselev, Alexander, 09/27/2023