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eic-projdet-pfrich-l - Re: [Eic-projdet-pfrich-l] pfRICH services sanity check

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  • From: "Aschenauer, Elke" <elke AT bnl.gov>
  • To: "Kiselev, Alexander" <ayk AT bnl.gov>
  • Cc: "eic-projdet-pfrich-l AT lists.bnl.gov" <eic-projdet-pfrich-l AT lists.bnl.gov>
  • Subject: Re: [Eic-projdet-pfrich-l] pfRICH services sanity check
  • Date: Fri, 11 Nov 2022 15:46:40 +0000

yes correct

cheers elke

On Nov 11, 2022, at 10:45, Kiselev, Alexander <ayk AT bnl.gov> wrote:

  Thank you Elke,

  this is exactly what I wanted to hear. We first assume that we can live with the individual cables (say, for HV this would be the thinnest 3kV-rated ones, five per HRPPD tile), one fiber per ASIC, and LV/cooling requirements matching some hypothetic power hungry electronics, as a worst case scenario. Then we start optimizing things, at a later stage. Correct?

  Regards,
    Alexander.






From: Aschenauer, Elke
Sent: Friday, November 11, 2022 10:33 AM
To: Kiselev, Alexander
Cc: Aschenauer, Elke; eic-projdet-pfrich-l AT lists.bnl.gov
Subject: Re: pfRICH services sanity check

Alexander,

thank you for filling the form and the comments, I agree with them, but nevertheless it would be so nice to once get something positive, 
to define patch panels or HV distribution boards and so on one needs first to know what one needs, this is what we are collecting and then we optimize based on the info.
This is not even version 0, and yes absolutely things depend on the readout electronics choice no doubt. 
But as you saw from the talk yesterday evening we will also work on this in parallel.
It would be wonderful if all would be know but it is not.
It is obvious from what we have right now, we need to use HV distribution boards, but the question where they can be located is also not easy.

Cheers elke


On Nov 11, 2022, at 10:10, Kiselev, Alexander <ayk AT bnl.gov> wrote:

  Dear Elke,

  I populated a "services wish list" backbone for pfRICH, and we will now proceed with the TBD items:

 I was wondering though, what are the sanity boundaries for these numbers. I mean at which point one should start worrying about a sheer quantity of the HV/LV/fiber connections, and grouping them into HV dividers, LV distribution panels and ASIC backplane concentrators?

  Another question is: which electronics should we take as a reference? Apparently almost everything in this table will depend on this choice, with numbers being different potentially by a factor of 1-10, easily (channel count per ASIC, mW/ch, etc).  

  Regards,
    Alexander.

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