U.S. ATLAS HL-LHC Upgrade LAr Level 2 and Level 3 Managers Mailing List

["Ma, Hong" <hma AT bnl.gov>]

Hi Tim,

 

                In your talk, page 52 still says 16 wafers.

                In any case, the text in that box on slide 52 seems to be redundant to the first bullet of the slide, except the number of needed wafers.

 

                Hong.

 

From: Tim Andeen <timothy.robert.andeen AT cern.ch>
Date: Sunday, July 21, 2019 at 1:30 PM
To: "Ma, Hong" <hma AT bnl.gov>
Cc: "usatlas-hllhc-lartl2l3-l AT lists.bnl.gov" <usatlas-hllhc-lartl2l3-l AT lists.bnl.gov>, John Parsons <parsons AT nevis.columbia.edu>
Subject: Re: [Usatlas-hllhc-lartl2l3-l] updates of NSF talk and other docs

 

Hi all, Just saw these comments. I just put most (all) of the suggestions, and I'll send some detailed answers before tomorrow morning EDT. Hong, I think you caught the big one re: the 16 vs 18 wafers .You're exactly right, it should be 18. I didn't realize that was what you were asking about in the BOE, also. I updated both in docdb.  

 

best, Tim

 

On Sun, Jul 21, 2019 at 2:23 AM Ma, Hong <hma AT bnl.gov> wrote:

Hi Tim,

                My comments on the your slides.

 

Slide 18: mention corresponding risk for choosing COTS ADC

 

Slide 25:

                “Engineering run of lpGBT”.

This does not fit our usual preprototype/prototype/preproduction/production sequence. Can you map it to our standard steps?

 

Slide 28: remove the lower right box “Document 216-v13”

Slide 30: “base on” à ” based on”

 

Slide 47: “10 main FEE risks”

                But the total of risks in backup slides 65 and 66 is 11.

 

Slide 49: indicate these 4 are the main risks, not all risks.

 

Slide 51:  “estimate 16 wafers needed.”

 

                This is the same question I had for BOE.  According to Table 7 in BOE, each wafer give 3879 chips. Then 69000 chips requires 69000/3879=17.8 = 18 wafers.

 

                (Slide 55 mentions 16 wafers too)

 

Slide 51: last bullet: “75 wafers” à”25 wafers”

                Slide 58 mentions 75 wafers too.

 

Slide 26 & 59:

   “Optical links Prototypes also finished by start of MREFC. lpGBT and VL+ ready, with final production version coming after MREFC. “

                In your BOE, you have: 

 

2. early 2020 – early 2021 – Data/control link prototypes

3. early 2021-late 2022 – Production Data/control links

 

                Are they consistent?

 

Slide 66:

                Why does the first risk have no probability (and no rank) ?

 

 

                Hong.

 

From: Usatlas-hllhc-lartl2l3-l <usatlas-hllhc-lartl2l3-l-bounces AT lists.bnl.gov> on behalf of John Parsons <parsons AT nevis.columbia.edu>
Date: Saturday, July 20, 2019 at 3:34 PM
To: "usatlas-hllhc-lartl2l3-l AT lists.bnl.gov" <usatlas-hllhc-lartl2l3-l AT lists.bnl.gov>
Subject: Re: [Usatlas-hllhc-lartl2l3-l] updates of NSF talk and other docs

 

 

Hi all,

 

                I looked quickly through other L3 talks

and give some comments below.

 

                                John

 

Tim

p. 19 - "At start of MREFC, Final Prototype ADC..."

(MREFC is missing.  Also, I have been calling them

"Final Prototypes" to stress "construction ready"

aspect, so let's all to that consistently

 

p. 25 - "Data and control...   conclude."

                - make a stronger stmt that these tests

"will demonstrate the design and implementation of

the data and control optical links for the FEB2"

to stress (again) the construction ready nature

 

p. 26 - typo "allows"

 

p. 28 - instead of "no changes" I would say the big

change is that the Analog Testboard has verified the

functionality of the interfaces

 

p. 30 - typo "closed"

 

p. 31 - you say "first test planned" but it is already

working

 

p. 34 - update table from my L2 talk

 

p. 37 - remove reduction until next slide, where it

is explained as a shift from FE to BE

 

p. 38 - add that shift from FE was done by reducing

67% to 54% in optics, as agreed in MOU

 

p. 39 - update pie chart

 

p. 41 - add that ASICs purchased through CERN Frame Contract

with TSMC

 

p. 43 - delete

 

p. 44 - update chart

 

p. 45-46 - need some text.  Consider using ATLAS review dates

 

pp. 47+48 - delete (those charts aren't made any more

 

p. 50 - make clear this is about optics

 

p. 51 - you are right, we now using 66.2% (need to

fix previous table of 100% on p. 34

and also anywhere where we might have said 67%)

 

p. 51 - say something about die size and how you get

number of wafers?

 

p. 58 - why 75 wafers here? (typo?)

 

p. 59 - typo "allows"

    - suggest to add "original construction" in addition

to Phase 1

 

p. 62 - delete, since you put earlier

 

p. 62 - not updated

 

- at end, you are supposed to have your 1 risk/page

risk pages (ie. in the format from the risk scrubbing)

 

 

 

Andy

p. 2 - delete red box

 

p. 4 - expand this to 3-4 slides; there is no need to

cram all this on one slide

                - also, update system block diag from my L2 talk

 

p. 5 - either fill in or delete (I don't think we need

names of people, but you need to say somewhere that

SBU/UAz did similar tasks in Ph 1

 

p. 6 - don't mix "carrier" and "main"; choose one

    - stress that functionality for US is the same,

just the details of the h/w implementation has changed

(we need to rely on Ph. 1 experience to argue we

are "construction ready", so promote the analogy

from Ph 1 to HL-LHC)

 

p. 8 - you have space to make fig a bit bigger (and more

readable)

 

p. 9 - change title to "PreMREFC/MREFC Boundary"

   - we should discuss with PO how they want to handle

the 5 mo. float issue.  They have said in past they would

like to try funding the sRTM v1 fab already in preMREFC,

but I don't know if they still hope for that, and in

any case what they want us to say.  I will ask

   - also we need to be careful about MREFC and maturity

of design when it starts (ie. "construction ready".

You should end preMREFC bit saying Ph 1/eval board work/

design of v1 sRTM will deliver a design that meets the

FDR requirements.  Then MREFC will test v1, design and

test v2, do prototype, then pre(prod).  See the slide

in my L2 talk about this

 

p. 10+12 - need to fill in.  See slides in my L3 and Tim's

as examples

 

p. 14 - take new org chart from my L2 talk

  - too simplified view of partners?  (eg. f/w certainly

has many groups)

   - I would suggest to separate this from org chart

 

p. 15 - if not sure about this, remove for now

 

p. 17 - get new pie chart (but put it on p. 23 instead)

                - you need to add discussion of BCP-017 that

changed sRTM cost share from 67% to 100%, in agreement

with LAr MOU

 

pp. 18+20 - get new graphics

 

p. 19 - say something about how SBU qualifies vendors

and will choose (see my L3 as an example)

 

p. 21+22+23 - need to update

 

- for drilldown slides, state which Attachment from BOE

in each case. Also put a box(es) around the number(s)

you are extracting from each, to guide the reviewers

 

- rather than just keep saying the numbers are wrong,

I suggest you provide explanation early on.  ie. cost

share was changed from 67% to 100%, but error made

using 2/3 instead, so numbers are very slightly off

but will be brought into exact agreement before FDR

 

- also, for each of the costs you need you have

justified, you need to show the tasks with those

costs in the Drilldown Report (ie. show how you

get from the BOE and quotes to the Drilldown Report)

 

p. 27 - to be written (look at our talks for examples)

 

p. 30+31 - need to do (including individual Risk slides)

 

 

On 7/20/19 2:42 PM, John Parsons wrote:

Hi all,

      After Friday's walkthrough of my L2 talk, I

updated the slides and posted a new version on this Tuesday's

agenda page at https://indico.bnl.gov/event/6491/.  A

reminder that we will go through the various L3 talks

during the meeting.  If anyone can take a look and

send comments, that would be helpful.

      Andy/Tim, have you updated your

talks after Hong's comments and uploaded a new version

to that indico page?

      We also need to get the updated BOEs into docdb.

Andy/Tim, let me know when you have done that.  Everyone has

implmented Hong's comments?  Let's archive the latest BOE

also on the same indico page as the L3 talks; I see Andy

has already done that.  I just put mine there also.

      Regards,

          John

 

--

______________________________________________________________________

 

John Parsons

Nevis Labs,                          Email: parsons AT nevis.columbia.edu

  Columbia University      Phone: (914) 591-2820

P.O. Box 137                       Fax: (914) 591-8120

Irvington, NY 10533         WWW: https://urldefense.proofpoint.com/v2/url?u=http-3A__www.nevis.columbia.edu_-7Eparsons_&d=DwIDaQ&c=aTOVZmpUfPKZuaG9NO7J7Mh6imZbfhL47t9CpZ-pCOw&r=DSVO6Re8kg14S-cQbkBC2zfSx6Yt2GtkcD3fTWOeyfXXTwIA3TKWV-phDKykUKDr&m=Gc8m38egb9oL2Sn386z-0_MuxgrRivvmHVWDp9R10vc&s=95qLnyb8qKCE3SvEMKoG3kUx5QpzS86FyOjglqddbcs&e=          

 

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Tim Andeen
Assistant Professor, Department of Physics
College of Natural Sciences
The University of Texas at Austin
Austin, TX 78712-1192
web: tandeen.web.cern.ch
office (TX): PMA 10.208
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