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["Capotosto, Michael" <capotosto AT bnl.gov>]

Gerard, 

That is correct. I believe we just need to re-number a few pairs of the test 
stand cable. For the four test boards we made with the old connectors in 
March/April, I believe the pairs in question would need to be re-soldered or 
re-pinned in the correct position.

--Mike

-----Original Message-----
From: Star-fst-l <star-fst-l-bounces AT lists.bnl.gov> On Behalf Of Gerard Visser
Sent: Thursday, October 17, 2019 11:48 AM
To: star-fst-l AT lists.bnl.gov
Subject: Re: [Star-fst-l] T-Board V2.1 Assembly (Cable Pinout/Schematic 
Questions)

hi guys,
        I can join such a meeting tomorrow, yes. Mike I didn't look at all 
your attachments yet, but the executive summary is nothing wrong that cannot 
be resolved by the mapping of soldering the cable wires to the board, is that 
correct? I hope... ??

        Gerard

On 10/17/2019 11:45 AM, flemming videbaek wrote:
> Hi
> 
> Would it be possible to have a meeting (remote) on this tomorrow 
> Friday pref in the morning.
>   - I would like to understand
> a) what went wrong here (my interpretaation of mike e-mail)
> b) what is the corret design
> c) who/when will it be done
> c) signoff before we proceed as its clearly not ready for production.
> 
> best Flemming
> 
> PS currently on way back fom DNP
> 
> 
> 
> Flemming Videbaek
> senior scientist
> videbaek @ bnl.gov <http://bnl.gov>
> Brookhaven National Lab
> Physics Department
> Bldg 510D
> Upton, NY 11973
> 
> phone: 631-344-4106
> cell     :  631-681-1596
> 
> 
> 
> 
> 
> 
>> On Oct 17, 2019, at 11:37, Capotosto, Michael <capotosto AT bnl.gov 
>> <mailto:capotosto AT bnl.gov>> wrote:
>>
>> Zhenyu and All,
>> Not sure who to address this to - I've asked the vendor to hold off 
>> on putting the test stand cables on the T-board, as I've noticed some 
>> discrepancies.
>> The attached Excel spreadsheet from Steve Valentino was used when 
>> ordering the test stand cables. Each wire/pair is labeled using the 
>> "Via Ref Des" column, in column "G", which corresponds to the D-Sub 
>> connector pin listed in column A.
>> When compared to the schematic for T-Board*_V2.0_*the Via Ref Des is 
>> incorrect
>> - the correct values according to the schematic are listed in Column 
>> I. This affected only OUT0 through OUT3. They are in reverse order, 
>> and some also have polarity reversed. This affects the first V2.0 test 
>> T-Boards we assembled.
>> Zhenyu, I believe these were sent to you, if so just be aware.
>> When compared to the T-Board*_V2.1_*the Via Ref Des is incorrect - 
>> the correct values according to the schematic are listed in Column J. 
>> This affected only
>> OUT0 through OUT2. OUT3 is correctly labeled. OUT0 through OUT2 all 
>> have polarity reversed.
>> I do not know the reason for the Via Ref Des changes between 
>> schematic/pcb revisions, or why the spreadsheet appears incorrect 
>> for*both**V2.0**and**V2.1*.
>> I would appreciate it if someone could tell me if my assumption 
>> regarding the correct labeling for the cable should be what I’ve 
>> listed in Column J, and if not let me know what it should be.
>> Thank you,
>> Mike Capotosto
>> <FST_Inner_cable_Test_Stand_Version_5MAr19_EDIT_10-17-2019.pdf><FST_I
>> nner_cable_Test_Stand_Version_5MAr19_EDIT_10-17-2019.xlsx><T-Board_v2
>> _1.pdf><T-Board_v2_sch.pdf>__________________________________________
>> _____
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