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star-fst-l - Re: [Star-fst-l] T-Board V2.1 Assembly (Cable Pinout/Schematic Questions)

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  • From: Zhenyu Ye <yezhenyu2003 AT gmail.com>
  • To: "Capotosto, Michael" <capotosto AT bnl.gov>
  • Cc: "star-fst-l AT lists.bnl.gov" <star-fst-l AT lists.bnl.gov>
  • Subject: Re: [Star-fst-l] T-Board V2.1 Assembly (Cable Pinout/Schematic Questions)
  • Date: Thu, 17 Oct 2019 13:36:42 -0500



> On Oct 17, 2019, at 12:49 PM, Capotosto, Michael <capotosto AT bnl.gov> wrote:
>
> Zhenyu,
>
>> Mike, in your file
>> FST_Inner_cable_Test_Stand_Version_5MAr19_EDIT_10-17-2019.pdf
>> do I understand correctly that you think the "Via Ref Des” given in
>>
>> 1. Column G are wrong for T2.0 ?
>> 2. Column I are correct for T2.0 ?
>> 3. Column J are correct for T2.1 ?
>
> Yes, this is what I compiled, assuming that the D-Sub pins and Signal Names
> are correct for what's connecting on either end.
>
>
>
>> and who wrote these columns
>> 1, by Steve in a file FST_Inner_cable_Test_Stand_Version_5MAr19.pdf (I am
>> guessing by the pdf file name)?
>> 2/3. by You ?
>
> Yes, Steve authored the original document, it initially had a few extra
> pages which I've removed (Part numbers for test cables). I organized by
> pairs, and added Columns I and J.
>
>
>
>> Do you have a similar picture as that in the Tab “T-board pinout
>> labelling” of the file
>> https://drupal.star.bnl.gov/STAR/system/files/FST_Inner_cable_Test_Stand_Version_26APR19.xlsx
>> but for T-board 2.1 (“2019-07-12”)?
>
> I do not, I was going to make a similar picture for T-Board V2.1, but
> noticed these pin changes beforehand, and wanted to confirm. This picture,
> along with Column G of FST_Inner_cable_Test_Stand_Version_5MAr19.pdf were
> used to solder the test stand cable to the V2.0 T-Boards you currently have.

This looks like a mistake, and the correct file for T-board 2.0 would be
https://drupal.star.bnl.gov/STAR/system/files/FST_Inner_cable_Test_Stand_Version_26APR19.xlsx

>
>
>
>> Looking at the labeling of the vias on the “2019-03-04” and “2019-07-12”
>> T-boards, it seems that the positions of the vias for OUT_0-3 are
>> reversed, i.e. OUT_0 -> OUT_3, OUT_1 -> OUT_2, OUT_2 -> OUT_1, OUT_3 ->
>> OUT_0.
>
> Yes, this is correct. I’ve attached a picture of the V2.0 T-Board and V2.1
> T-Board side by side for clarity.

Ok. Maybe one thing we need is a file like
https://drupal.star.bnl.gov/STAR/system/files/FST_Inner_cable_Test_Stand_Version_26APR19.xlsx
but for T-board 2.1, and have someone to check it independently.

Zhenyu

>
> --Mike
>
> -----Original Message-----
> From: Zhenyu Ye <yezhenyu2003 AT gmail.com>
> Sent: Thursday, October 17, 2019 1:13 PM
> To: Capotosto, Michael <capotosto AT bnl.gov>
> Cc: Gerard Visser <gvisser AT indiana.edu>; star-fst-l AT lists.bnl.gov
> Subject: Re: [Star-fst-l] T-Board V2.1 Assembly (Cable Pinout/Schematic
> Questions)
>
>
>
>> On Oct 17, 2019, at 11:23 AM, Capotosto, Michael <capotosto AT bnl.gov> wrote:
>>
>> Gerard,
>>
>> That is correct. I believe we just need to re-number a few pairs of the
>> test stand cable. For the four test boards we made with the old connectors
>> in March/April, I believe the pairs in question would need to be
>> re-soldered or re-pinned in the correct position.
>
> Mike, in your file
> FST_Inner_cable_Test_Stand_Version_5MAr19_EDIT_10-17-2019.pdf
> do I understand correctly that you think the "Via Ref Des” given in
>
> 1. Column G are wrong for T2.0 ?
> 2. Column I are correct for T2.0 ?
> 3. Column J are correct for T2.1 ?
>
> and who wrote these columns
> 1, by Steve in a file FST_Inner_cable_Test_Stand_Version_5MAr19.pdf (I am
> guessing by the pdf file name)?
> 2/3. by You ?
>
> Yes, I received four cables with T-board 2.0 (labelled “2019-03-04") in
> May. The corresponding files from Steve were uploaded on April 29 onto
> https://drupal.star.bnl.gov/STAR/blog/yezhenyu/forward-silicon-tracker-cables
>
>
> One of the files
> https://drupal.star.bnl.gov/STAR/system/files/FST_Inner_cable_Test_Stand_Version_26APR19.xlsx
> lists the Via Ref Des, which are the same as Column I in your file
>
> Do you have a similar picture as that in the Tab “T-board pinout labelling”
> of the file
> https://drupal.star.bnl.gov/STAR/system/files/FST_Inner_cable_Test_Stand_Version_26APR19.xlsx
> but for T-board 2.1 (“2019-07-12”)?
>
> Looking at the labeling of the vias on the “2019-03-04” and “2019-07-12”
> T-boards, it seems that the positions of the vias for OUT_0-3 are reversed,
> i.e. OUT_0 -> OUT_3, OUT_1 -> OUT_2, OUT_2 -> OUT_1, OUT_3 -> OUT_0.
>
> Zhenyu
>
>
>>
>> --Mike
>>
>> -----Original Message-----
>> From: Star-fst-l <star-fst-l-bounces AT lists.bnl.gov> On Behalf Of
>> Gerard Visser
>> Sent: Thursday, October 17, 2019 11:48 AM
>> To: star-fst-l AT lists.bnl.gov
>> Subject: Re: [Star-fst-l] T-Board V2.1 Assembly (Cable
>> Pinout/Schematic Questions)
>>
>> hi guys,
>> I can join such a meeting tomorrow, yes. Mike I didn't look at all
>> your attachments yet, but the executive summary is nothing wrong that
>> cannot be resolved by the mapping of soldering the cable wires to the
>> board, is that correct? I hope... ??
>>
>> Gerard
>>
>> On 10/17/2019 11:45 AM, flemming videbaek wrote:
>>> Hi
>>>
>>> Would it be possible to have a meeting (remote) on this tomorrow
>>> Friday pref in the morning.
>>> - I would like to understand
>>> a) what went wrong here (my interpretaation of mike e-mail)
>>> b) what is the corret design
>>> c) who/when will it be done
>>> c) signoff before we proceed as its clearly not ready for production.
>>>
>>> best Flemming
>>>
>>> PS currently on way back fom DNP
>>>
>>>
>>>
>>> Flemming Videbaek
>>> senior scientist
>>> videbaek @ bnl.gov <http://bnl.gov>
>>> Brookhaven National Lab
>>> Physics Department
>>> Bldg 510D
>>> Upton, NY 11973
>>>
>>> phone: 631-344-4106
>>> cell : 631-681-1596
>>>
>>>
>>>
>>>
>>>
>>>
>>>> On Oct 17, 2019, at 11:37, Capotosto, Michael <capotosto AT bnl.gov
>>>> <mailto:capotosto AT bnl.gov>> wrote:
>>>>
>>>> Zhenyu and All,
>>>> Not sure who to address this to - I've asked the vendor to hold off
>>>> on putting the test stand cables on the T-board, as I've noticed some
>>>> discrepancies.
>>>> The attached Excel spreadsheet from Steve Valentino was used when
>>>> ordering the test stand cables. Each wire/pair is labeled using the
>>>> "Via Ref Des" column, in column "G", which corresponds to the D-Sub
>>>> connector pin listed in column A.
>>>> When compared to the schematic for T-Board*_V2.0_*the Via Ref Des is
>>>> incorrect
>>>> - the correct values according to the schematic are listed in Column
>>>> I. This affected only OUT0 through OUT3. They are in reverse order,
>>>> and some also have polarity reversed. This affects the first V2.0 test
>>>> T-Boards we assembled.
>>>> Zhenyu, I believe these were sent to you, if so just be aware.
>>>> When compared to the T-Board*_V2.1_*the Via Ref Des is incorrect -
>>>> the correct values according to the schematic are listed in Column J.
>>>> This affected only
>>>> OUT0 through OUT2. OUT3 is correctly labeled. OUT0 through OUT2 all
>>>> have polarity reversed.
>>>> I do not know the reason for the Via Ref Des changes between
>>>> schematic/pcb revisions, or why the spreadsheet appears incorrect
>>>> for*both**V2.0**and**V2.1*.
>>>> I would appreciate it if someone could tell me if my assumption
>>>> regarding the correct labeling for the cable should be what I’ve
>>>> listed in Column J, and if not let me know what it should be.
>>>> Thank you,
>>>> Mike Capotosto
>>>> <FST_Inner_cable_Test_Stand_Version_5MAr19_EDIT_10-17-2019.pdf><FST_
>>>> I
>>>> nner_cable_Test_Stand_Version_5MAr19_EDIT_10-17-2019.xlsx><T-Board_v
>>>> 2
>>>> _1.pdf><T-Board_v2_sch.pdf>_________________________________________
>>>> _
>>>> _____
>>>> Star-fst-l mailing list
>>>> Star-fst-l AT lists.bnl.gov <mailto:Star-fst-l AT lists.bnl.gov>
>>>> https://lists.bnl.gov/mailman/listinfo/star-fst-l
>>>
>>>
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>
> <V2 vs V2_1 T-Board.jpg>





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