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["Ye, Zhenyu" <yezhenyu AT uic.edu>]

Sent from my iPhone



Sent from my iPhone
> On Nov 6, 2019, at 11:20 AM, Gerard Visser <gvisser AT indiana.edu> wrote:
> 
> hi Zhenyu,
>   Ok so the pedestal widths and all from the chips that worked were normal 
> (i.e. width < that in IST, since no detector capacitance, and responding 
> about as in IST to VPSP control)?

Hi Gerard,

Yes

> I did miss hearing that I guess, but it is certainly good news.
>   It would be nice if we could test full inner hybrid properly assembled 
> before ordering v2.2 outer ones, but indeed if that isn't feasible this 
> should be accepted, it should be a small risk.

Indeed, as we discussed a couple of weeks ago, this is not feasible because 
of tight project schedule. We need to order new outer hybrids so that we can 
test outer sensors, in parallel to inner ones

Zhenyu

> 
>   - Gerard
> 
> 
> 
>>> On 11/5/2019 9:35 PM, Ye, Zhenyu wrote:
>>> Sent from my iPhone
>>> On Nov 6, 2019, at 10:23 AM, Gerard Visser <gvisser AT indiana.edu> wrote:
>>> 
>>> Hi Zhenyu,
>>>   I'll try to look over all the various things I was supposed to have 
>>> looked over by the time of the meeting.
>> This will be excellent.
>>>   In meanwhile, let me again ask if possible we can see a few pictures 
>>> documenting that things really fit w/ the hybrid to T-board connectors 
>>> when mounted (or simulated mounted) on the mechanical structure, I think 
>>> this would be wise we see this before the v2.2 hybrid production. Of 
>>> course if it is impossible to check this at this time deciding to proceed 
>>> anyway may be necessary.
>> I chatted with Yi about it last week and this morning and he will send 
>> pictures when he is back at NCKU.
>>>   Similarly I think it would be advisable we get pedestals out of one of 
>>> the existing hybrids if possible before ordering v2.2, but if that is 
>>> infeasible I guess it is a small risk.
>> If you recall, Andres mounted and manually wire-bonded some chips onto the 
>> first version of hybrids and with test cables saw good pedestals from 2 of 
>> them. The reason for not seeming the other chips could be wire-bonding or 
>> something else but we don't have the capability to identify the cause 
>> without reliable wire-bonding. The latter will become available with the 
>> incoming prototype assembly at Fermilab, for which we do need the new 
>> hybrids.
>> Zhenyu
>>> 
>>>   Gerard
>>> 
>>> 
>>>> On 11/5/2019 8:27 PM, Ye, Zhenyu wrote:
>>>> Dear all,
>>>> We will have a weekly FST meeting this Thursday 9am BNL time. The 
>>>> meeting agenda and bluejeans info can be found at
>>>> https://drupal.star.bnl.gov/STAR/blog/yezhenyu/forward-silicon-tracker-weekly-meeting
>>>> 1. Hybrid, T-board, Inner Signal Cable - Jianing, Gerard, Mike
>>>> 2. Mechanical structure - Yi, Han-Sheng
>>>> 3. Module Assembly at Fermilab - Zhenyu
>>>> 4. BNL Test stand - Prithwish, Hu
>>>> 5. Simulation - Te-Chuan, Krishan
>>>> I think we have to discuss any remaining issue if any and decide on the 
>>>> v2.2 hybrid production, which may delay the whole project. We should 
>>>> also hear the status of mechanical structure from Yi. If there is 
>>>> anything else to report/discuss, please let me know.
>>>> Best
>>>> Zhenyu
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