ePIC pfRICH electronics mailing list

["Kiselev, Alexander" <ayk AT bnl.gov>]

  Dear All,

  now that the FMC board purchase order request is placed in the system here at BNL (and the manufacturer actually started the EQ procedure with us), let's turn back to the other three parts of the V0 configuration:

  (1) Pierrick, when do you think you can be ready with the ASIC board design?

  (2) Gabor, Daniel and Miklos: since adding thermistors to the ASIC board is pretty much excluded in V0 iteration (it better be out for manufacturing as soon as ready), can we do a meaningful test of this safety feature functionality mounting them onto the FPGA board? Will we need them also on the FPGA board in V1? Then what model, how many and where? As to the V1, Daniel would like to place at least one per a pair of ASICs (if not one per ASIC). Will we have enough pins in Samtec connectors to allow for this in V1 iteration, at all?

  (2a) Gabor, what are your current timelines to finish the FPGA board? Do we still need to discuss anything substantially new other than the cooling system interface?

  (3) Daniel, Gabor: are we all clear about the layout of the additional FPGA cooling plates with fins? Or we wait until Daniel has time to distribute a complete cooling setup model? Gabor, do you have a preliminary CAD model of the FPGA board, to help Daniel?

  (3a) Daniel: are we going to provide power to the fan in V0 via a separate cable?

  Cheers,

    Alexander.