ePIC pfRICH electronics mailing list

[Pierrick Dinaucourt <pdinaucourt AT omega.in2p3.fr>]

Dear Alexander,

for me it's ok, the design is over. I check the last point and I'm speaking with the manufacturer to correct some details. I'll share with you the documents, Gerber, schema and step asap.

The order will be send this week and after it's 3 weeks to have the PCB. We think also for the assembly and the number of Asic we need. I'm not sure we can provide more than 50 Asics actually now. With this we can do one complete card with 16 asics, 2 others with 8 asics and 4 cards with 4 asics.

Regards

Pierrick

Le 21/11/2023 à 03:13, Kiselev, Alexander a écrit :

          Dear All,
      
        
      
      
          now that the FMC board purchase order request is placed in the
        system here at BNL (and the manufacturer actually started the EQ
        procedure with us), let's turn back to the other three parts of
        the V0 configuration:
      
        
      
      
          (1) Pierrick, when do you think you can be ready with
        the ASIC board design?
      
        
      
      
          (2) Gabor, Daniel and Miklos: since
        adding thermistors to the ASIC board is pretty much excluded in
        V0 iteration (it better be out for manufacturing as soon as
        ready), can we do a meaningful test of this safety feature
        functionality mounting them onto the FPGA board? Will we need
        them also on the FPGA board in V1? Then what model, how many and
        where? As to the V1, Daniel would like to place at least one per
        a pair of ASICs (if not one per ASIC). Will we have enough pins
        in Samtec connectors to allow for this in V1 iteration, at all?
      
        
      
      
          (2a) Gabor, what are your current timelines to finish
        the FPGA board? Do we still need to discuss anything
        substantially new other than the cooling system interface?
      
      
        
      
      
          (3) Daniel, Gabor: are we all clear about the
        layout of the additional FPGA cooling plates with fins? Or we
        wait until Daniel has time to distribute a complete cooling
        setup model?
        Gabor, do you have a preliminary CAD model of the FPGA
        board, to help Daniel?
      
        
      
      
          (3a) Daniel: are we going to provide power to the fan
        in V0 via a separate cable?
      
      
        
      
      
          Cheers,
      
            Alexander.
      
        
      
      
        
      
      
        
      
    
-- 
Pierrick Dinaucourt
PCB Designer
Laboratoire OMEGA
Unité CNRS-Polytechnique
tél: 01-69-33-89-83