ePIC pfRICH electronics mailing list

["Kiselev, Alexander" <ayk AT bnl.gov>]

  Hi Gabor,

  Sounds good as well! 

  Concerning the temperature control: can we still make use of the V0 FPGA board, to start adjusting the firmware, and have a better idea of what (and how) needs to be added to the V1 ASIC board? If there should be a dedicated I2C bus somewhere, can / should we implement its prototype in the FPGA board design now? Miklos, can you be more specific about interference with the ASIC I2C bus? Pierrick: if we are not using ASICs for these purposes, what are other reasonable options for the V1 iteration? 

  Cheers,

    Alexander.

---

From: nagy g <hunagabo AT gmail.com>
Sent: Tuesday, November 21, 2023 1:00 PM
To: Pierrick Dinaucourt <pdinaucourt AT omega.in2p3.fr>
Cc: Kiselev, Alexander <ayk AT bnl.gov>; Cacace, Daniel <dcacace AT bnl.gov>; Miklos Czeller <miklos.czeller AT mediso.com>; Camarda, Timothy via Eic-projdet-pfrich-electronics-l <eic-projdet-pfrich-electronics-l AT lists.bnl.gov>
Subject: Re: Final modifications to the V0 FPGA board

 

Hello Alexander,

(2) We do not necessary need additional pins, if we use a digtal, in this case I2C temerature sensors.

I mean if Pierric can add a temp sensor to the next version of ASICs board like TMP114NDIYMTR to every I2C line (like SDA_Gx, SCL_Gx) then we could use one sensor for every two ASICs withouth any change on ERM5 connector pinout. (if +/-0.5C accuracy is enough:))

https://hu.mouser.com/ProductDetail/Texas-Instruments/TMP114NDIYMTR?qs=t7xnP681wgWJtFGgf4opSA%3D%3D

(2a) No, I think the FPGA board is well defined, so I do not need anything at the moment. (With the following differences to the original plan:

- We agreed to use a DataIO connector for the Ethernet, instead of RJ45 connector

- and based on the latest information about the AISCs current I will decrease the max +1V2A to 4A

(Originally at the FMC board I prepared to 1A analog and 1A digital for each ASIC, which could be my missunderstanding, but last time when we talk Pierric sad that it is only 1A together, which means I can remove half of the LDO from the FPGA card.))

(3) I am still working on the schematic, and there is no CAD model what I could share (I can if you wish, but it is too early to work with it), but hopefully end of this week I will have a "final one" with the first iteration of placement. So, basically I still try to keep the three weeks.

Best Regards, gabor

Pierrick Dinaucourt <pdinaucourt AT omega.in2p3.fr> ezt írta (időpont: 2023. nov. 21., K, 10:29):

Dear Alexander,

for me it's ok, the design is over. I check the last point and I'm speaking with the manufacturer to correct some details. I'll share with you the documents, Gerber, schema and step asap.

The order will be send this week and after it's 3 weeks to have the PCB. We think also for the assembly and the number of Asic we need. I'm not sure we can provide more than 50 Asics actually now. With this we can do one complete card with 16 asics, 2 others with 8 asics and 4 cards with 4 asics.

Regards

Pierrick

Le 21/11/2023 à 03:13, Kiselev, Alexander a écrit :

  Dear All,

  now that the FMC board purchase order request is placed in the system here at BNL (and the manufacturer actually started the EQ procedure with us), let's turn back to the other three parts of the V0 configuration:

  (1) Pierrick, when do you think you can be ready with the ASIC board design?

  (2) Gabor, Daniel and Miklos: since adding thermistors to the ASIC board is pretty much excluded in V0 iteration (it better be out for manufacturing as soon as ready), can we do a meaningful test of this safety feature functionality mounting them onto the FPGA board? Will we need them also on the FPGA board in V1? Then what model, how many and where? As to the V1, Daniel would like to place at least one per a pair of ASICs (if not one per ASIC). Will we have enough pins in Samtec connectors to allow for this in V1 iteration, at all?

  (2a) Gabor, what are your current timelines to finish the FPGA board? Do we still need to discuss anything substantially new other than the cooling system interface?

  (3) Daniel, Gabor: are we all clear about the layout of the additional FPGA cooling plates with fins? Or we wait until Daniel has time to distribute a complete cooling setup model? Gabor, do you have a preliminary CAD model of the FPGA board, to help Daniel?

  (3a) Daniel: are we going to provide power to the fan in V0 via a separate cable?

  Cheers,

    Alexander.

-- 
Pierrick Dinaucourt
PCB Designer
Laboratoire OMEGA
Unité CNRS-Polytechnique
tél: 01-69-33-89-83