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[Christophe de La Taille <taille AT in2p3.fr>]

dear Alexander,

the chips can operate without problems at 50°C or more, we may also use parameters that reduce the power dissipation (no ToT...).

Discussing with Pierrick here, we propose to fisrt assemble 3PCBs : one with 2 chips, one with 4 and one with 8, essentially for the power and digital tests.  The ones with 2 and 4 chips will focus on the noise and the timing performance.

Best :  Christophe

On 27/11/2023 21:20, Kiselev, Alexander via Eic-projdet-pfrich-electronics-l wrote:

          Hi Gabor,
      
        
      
      
          There are few remaining questions related to the temperature
        monitoring in this V0 iteration:
      
        
      
      
          (1) can we add at least one permanently mounted temperature
        sensor (on the FPGA board), provisions to attach at least one
        remote sensor (placed next to one of the ASICs), and some
        minimal I2C circuitry to handle those by FPGA, in order to get a
        feeling of how this all will look in V1?
      
        
      
      
          (2) can you point Daniel to other expected hot spots on the
        FPGA board (say related to power convertors, ethernet-related
        circuitry, etc)?
      
        
      
      
          Also, Christophe, Pierrick: remind us please,
        what is the safe temperature range we are going to operate the
        ASICs?
      
        
      
      
          Cheers,
      
            Alexander.
      
        
      
      
      
    
-- 
--
Christophe de LA TAILLE
OMEGA CNRS/IN2P3 Micro-Electronics Design Lab
Professor of micro-electronics at Ecole Polytechnique
Ecole Polytechnique  F91128 Palaiseau France
+33 16933 8998