ePIC pfRICH electronics mailing list

[Christophe de La Taille <taille AT in2p3.fr>]

dear Tonko,

thanks for your message, I am sorry I was not aware of this development 
and we can certainly take into account when we make an iteration of the 
testboards and also for the next series of chips.  As we are not 
designing here the FPGA boards here at OMEGA, this is probably more 
addressed to the readout side, but we'll adapt to the FMC pinout 
recommendations.   Best regards : Christophe

On 28/11/2023 15:29, Tonko Ljubicic wrote:
> Hello,
>
> I'm new to this mailing list so perhaps this was discussed before.
>
> In short: we are designing an RDO Prototype which is expected to be
> of value to all frontend groups. We would like to make it as generic as 
> possible
> and to do that we added a FMC connector so that we can readout various
> frontend ASICs in the manner we all currently use FPGA development kits.
>
> Looking at the already existing ASIC test cards (e.g. EICROC0, H2GCROC, etc)
> we noticed a lot of (unsurprising) pin clashes on the FMC connector which made
> it practically impossible to use the RDO Prototype with all of them.
>
> What I am after (and I talked to Miklos, for example) is a unified approach
> to the FMC pinouts and (if lucky) signal standards. The only really critical
> pins are the clocks going _into_ your testboards because they will be fed
> directly by very low jitter PLLs from my RDO Prototype so I can't just
> "reprogram" them depending on various boards.
>
> What do you think? I can give you a short presentation with the details
> if anyone cares.
>
>             -- Tonko
>
>
> On Tue, Nov 28, 2023 at 1:58 PM Christophe de La Taille via
> Eic-projdet-pfrich-electronics-l
> <eic-projdet-pfrich-electronics-l AT lists.bnl.gov> wrote:
> > dear Alexander,
> >
> > the chips can operate without problems at 50°C or more, we may also use 
> > parameters that reduce the power dissipation (no ToT...).
> >
> > Discussing with Pierrick here, we propose to fisrt assemble 3PCBs : one with 
> > 2 chips, one with 4 and one with 8, essentially for the power and digital 
> > tests.  The ones with 2 and 4 chips will focus on the noise and the timing 
> > performance.
> >
> > Best :  Christophe
> >
> >
> >
> > On 27/11/2023 21:20, Kiselev, Alexander via Eic-projdet-pfrich-electronics-l 
> > wrote:
> >
> >    Hi Gabor,
> >
> >    There are few remaining questions related to the temperature monitoring in 
> > this V0 iteration:
> >
> >    (1) can we add at least one permanently mounted temperature sensor (on the 
> > FPGA board), provisions to attach at least one remote sensor (placed next to 
> > one of the ASICs), and some minimal I2C circuitry to handle those by FPGA, in 
> > order to get a feeling of how this all will look in V1?
> >
> >    (2) can you point Daniel to other expected hot spots on the FPGA board 
> > (say related to power convertors, ethernet-related circuitry, etc)?
> >
> >    Also, Christophe, Pierrick: remind us please, what is the safe temperature 
> > range we are going to operate the ASICs?
> >
> >    Cheers,
> >      Alexander.
> >
> >
> > --
> > --
> > Christophe de LA TAILLE
> > OMEGA CNRS/IN2P3 Micro-Electronics Design Lab
> > Professor of micro-electronics at Ecole Polytechnique
> > Ecole Polytechnique  F91128 Palaiseau France
> > +33 16933 8998
> >
> > --
> > Eic-projdet-pfrich-electronics-l mailing list
> > Eic-projdet-pfrich-electronics-l AT lists.bnl.gov
> > https://lists.bnl.gov/mailman/listinfo/eic-projdet-pfrich-electronics-l

--
--
Christophe de LA TAILLE
OMEGA CNRS/IN2P3 Micro-Electronics Design Lab
Professor of micro-electronics at Ecole Polytechnique
Ecole Polytechnique  F91128 Palaiseau France
+33 16933 8998