ePIC pfRICH electronics mailing list

["Kiselev, Alexander" <ayk AT bnl.gov>]

  Hi Daniel,

  can you confirm we use a couple of these (on board ones) in this first iteration, and be happy?

I'd suggest to place them on the bottom side of the FPGA board, so that one can establish a direct contact to the ASIC board cold plate. The rest is a matter of a calibration of how much the temperature of these sensors is different from any other spots on the assembly.

  Cheers,

    Alexander.

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From: nagy g <hunagabo AT gmail.com>
Sent: Tuesday, November 28, 2023 10:55 AM
To: Kiselev, Alexander <ayk AT bnl.gov>
Cc: Camarda, Timothy via Eic-projdet-pfrich-electronics-l <eic-projdet-pfrich-electronics-l AT lists.bnl.gov>
Subject: Re: Temperature monitoring in V0 & V1

 

Hi Alexander,

(1) I can add this type of sensor with a minimal effort if this one is acceptable (new low voltage version of the 1820): https://www.ti.com/product/TMP1820

This is one small terminal on the board, and you can add several sensor to the same bus (with a quite good accuracy). It need a bit of FPGA coding but not a nightmare to use.

(2) I need a bit of time but I will send a picture with the marked hot spots today.

Br, gabor

Kiselev, Alexander <ayk AT bnl.gov> ezt írta (időpont: 2023. nov. 27., H, 21:20):

  Hi Gabor,

  There are few remaining questions related to the temperature monitoring in this V0 iteration:

  (1) can we add at least one permanently mounted temperature sensor (on the FPGA board), provisions to attach at least one remote sensor (placed next to one of the ASICs), and some minimal I2C circuitry to handle those by FPGA, in order to get a feeling of how this all will look in V1?

  (2) can you point Daniel to other expected hot spots on the FPGA board (say related to power convertors, ethernet-related circuitry, etc)?

  Also, Christophe, Pierrick: remind us please, what is the safe temperature range we are going to operate the ASICs?

  Cheers,

    Alexander.