ePIC pfRICH electronics mailing list

[Tonko Ljubicic <tonko AT bnl.gov>]

Hi Alexander,

What I'm after is a triviality: clocks connected to known FMC pins for
all testboards
in the _future_. Obviously, if the testboard already exists or is in
production, it is what it is and
there's no discussion anymore.

I am designing my board right now and I need to fix the FMC pinout by ~May 
2024.
So what I am after is to try to make sure all other testboards
currently in design
match a bunch of pins with me to the benefit of all.

Let me know the date/time and I'll gladly spend all of 10 minutes with
this simple
request :-)




On Tue, Nov 28, 2023 at 4:00 PM Kiselev, Alexander <ayk AT bnl.gov> wrote:
>
>   Hi Tonko,
>
>   whether it was a right or a wrong approach, but in order to speed up the 
> V0 iteration of our ASIC/FMC/FPGA board set, it was proposed to decouple 
> the design from any possible complications caused by either a streaming 
> readout functionality or potential delays typically caused by negotiations 
> defining things like a unified RDO interface you mentioned. For instance, 
> it is more or less clear that a "final" version of the HRPPD backplane will 
> not be based on two independent FPGA boards as it is now (though will be 
> the same in the V1 iteration early 2024). So be it. We needed a setup with 
> a sufficient functionality being ready for a beam test in late spring 2024, 
> as a main objective, and we are hopefully getting there.
>
>   Now that the V0 iteration is pretty much out for production, perhaps it's 
> a good time to consider things like the RDO interface, and at least clarify 
> what does it mean at this point (when HGCROCs have no streaming capability, 
> and EICROCs do not have high channel count yet). From my perspective, we 
> can discuss this in a context of EICROC1-based setup only, as a V2 
> iteration of the HRPPD backplane, towards the end of 2024, correct?
>
>   I think we can pick up a Friday 9am EST time slot for a short meeting, 
> either this or next week.
>
>   Cheers,
>     Alexander.
>
> ________________________________
> From: Eic-projdet-pfrich-electronics-l 
> <eic-projdet-pfrich-electronics-l-bounces AT lists.bnl.gov> on behalf of Tonko 
> Ljubicic via Eic-projdet-pfrich-electronics-l 
> <eic-projdet-pfrich-electronics-l AT lists.bnl.gov>
> Sent: Tuesday, November 28, 2023 9:29 AM
> To: Christophe de La Taille <taille AT in2p3.fr>
> Cc: eic-projdet-pfrich-electronics-l AT lists.bnl.gov 
> <eic-projdet-pfrich-electronics-l AT lists.bnl.gov>
> Subject: Re: [Eic-projdet-pfrich-electronics-l] Temperature monitoring in 
> V0 & V1
>
> Hello,
>
> I'm new to this mailing list so perhaps this was discussed before.
>
> In short: we are designing an RDO Prototype which is expected to be
> of value to all frontend groups. We would like to make it as generic as 
> possible
> and to do that we added a FMC connector so that we can readout various
> frontend ASICs in the manner we all currently use FPGA development kits.
>
> Looking at the already existing ASIC test cards (e.g. EICROC0, H2GCROC, etc)
> we noticed a lot of (unsurprising) pin clashes on the FMC connector which 
> made
> it practically impossible to use the RDO Prototype with all of them.
>
> What I am after (and I talked to Miklos, for example) is a unified approach
> to the FMC pinouts and (if lucky) signal standards. The only really critical
> pins are the clocks going _into_ your testboards because they will be fed
> directly by very low jitter PLLs from my RDO Prototype so I can't just
> "reprogram" them depending on various boards.
>
> What do you think? I can give you a short presentation with the details
> if anyone cares.
>
>            -- Tonko
>
>
> On Tue, Nov 28, 2023 at 1:58 PM Christophe de La Taille via
> Eic-projdet-pfrich-electronics-l
> <eic-projdet-pfrich-electronics-l AT lists.bnl.gov> wrote:
> >
> > dear Alexander,
> >
> > the chips can operate without problems at 50°C or more, we may also use 
> > parameters that reduce the power dissipation (no ToT...).
> >
> > Discussing with Pierrick here, we propose to fisrt assemble 3PCBs : one 
> > with 2 chips, one with 4 and one with 8, essentially for the power and 
> > digital tests.  The ones with 2 and 4 chips will focus on the noise and 
> > the timing performance.
> >
> > Best :  Christophe
> >
> >
> >
> > On 27/11/2023 21:20, Kiselev, Alexander via 
> > Eic-projdet-pfrich-electronics-l wrote:
> >
> >   Hi Gabor,
> >
> >   There are few remaining questions related to the temperature monitoring 
> > in this V0 iteration:
> >
> >   (1) can we add at least one permanently mounted temperature sensor (on 
> > the FPGA board), provisions to attach at least one remote sensor (placed 
> > next to one of the ASICs), and some minimal I2C circuitry to handle those 
> > by FPGA, in order to get a feeling of how this all will look in V1?
> >
> >   (2) can you point Daniel to other expected hot spots on the FPGA board 
> > (say related to power convertors, ethernet-related circuitry, etc)?
> >
> >   Also, Christophe, Pierrick: remind us please, what is the safe 
> > temperature range we are going to operate the ASICs?
> >
> >   Cheers,
> >     Alexander.
> >
> >
> > --
> > --
> > Christophe de LA TAILLE
> > OMEGA CNRS/IN2P3 Micro-Electronics Design Lab
> > Professor of micro-electronics at Ecole Polytechnique
> > Ecole Polytechnique  F91128 Palaiseau France
> > +33 16933 8998
> >
> > --
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