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Re: [Star-fst-l] Weekly FST meeting, August 10 9am (BNL time)

From: Gerard Visser <gvisser AT indiana.edu>
To: "Capotosto, Michael" <capotosto AT bnl.gov>, "Videbaek, Flemming" <videbaek AT bnl.gov>
Cc: "star-fst-l AT lists.bnl.gov" <star-fst-l AT lists.bnl.gov>
Subject: Re: [Star-fst-l] Weekly FST meeting, August 10 9am (BNL time)
Date: Wed, 12 Aug 2020 09:08:18 -0400

hi Mike,
I understand, and your solution seems fine though a bit more confusing (at least looking a bit more confusing on the documentation). It is a reasonable plan.
I think we should prepare one PPB and ABC board accordingly and they should be tested in the UIC setup. Zhenyu, do you agree this is best?
Sincerely,

Gerard

On 8/12/2020 8:43 AM, Capotosto, Michael wrote:

Hey Gerard, All,

If you're trying to find emails regarding this, it looks like Steve had me
make the modifications in April or May of 2019.

When I did the modification I cut *and lifted* a section of track for OUT8P and
OUT8N between those .1" pitch pads and the 50 pos d-sub - so we can't just
bridge it, we'd have to scrape the mask off and lay two pieces of magnet wire in.
It'd be rather labor intensive and time consuming to bring the PPB back to
original.

I'd propose a simpler solution:
1. We can remove the 28AWG jumpers installed in this picture
https://drupal.star.bnl.gov/STAR/system/files/FST%20Modifications%20to%20IST%20Patch%20Panel%20Board_4APR19.png
2. We bridge OUT8P and OUT10P, OUT8N and OUT10N on the PPB (8 and 10 are
adjacent, according to the silkscreen. They are a 0.1" pitch, so we can very
easily bridge with a 1206 0R resistor)
3. We make the modifications to the ABC board, using OUT10P/OUT10N
for the second bias voltage.

Other than this, I'll get a quote or two for the current ABC boards, that
should give us an idea of what it would cost if we wanted to do a respin with
the added BNCs. I'll think about how best we can add the BNC pigtails as well.

--Mike

-----Original Message-----
From: Star-fst-l <star-fst-l-bounces AT lists.bnl.gov> On Behalf Of videbaek
Sent: Tuesday, August 11, 2020 4:41 PM
To: Gerard Visser <gvisser AT indiana.edu>
Cc: star-fst-l AT lists.bnl.gov
Subject: Re: [Star-fst-l] Weekly FST meeting, August 10 9am (BNL time)

Hi Gerard,
thanks for your input. I just want to remind all that we have a plan for
checking out the full chain with the system in November or so connecting to
DAQ. We should take this opportunity to have mods done for a few boards so we
can run and exercise a (test) module in the Hall.

best F.

On 2020-08-11 16:34, Gerard Visser wrote:

hi Zhenyu & all,
I looked at all out schematics concerning the bias voltage
connections and things should work out very well. We have to un-do the
changes that we unfortunately made to all the PPB, which was not wise
to have done before we had a final plan. But it should be feasible.
And then we have to modify the ABC boards (18 of them) to cut two of
the signal pairs from the ARM connector and instead wire to two new
BNC conenctors (or to two cable pigtails to BNC connectors, would be
OK). It would be possible to build 18 new ABC boards instead, but the
D connectors if we use same high quality ones are rather expensive.
Mike should please consider the pro/con for modification vs. new ABC
boards.
Attached slides summarize the detector bias connections from the
detectors to the BNC connectors. Mike please check that I didn't get
something wrong, of course.
Let's call this decided, and get the PPB's back to their original
state, and modify one or a few of the ABC boards for the test
setup(s).
Sincerely,

Gerard

p.s. We should hi-pot the bias connections (up to T-board, unplugged
from the hybrids) to some test voltage that makes sense (TBD) based on
maximum operating voltage you expect. What is that max operating
voltage?

On 8/10/2020 1:25 PM, Ye, Zhenyu wrote:

Minutes:

1. Flemming showed a draft of committee recommendations. He will have
a meeting with the committee this afternoon. Expect to have a final
version soon.

2. Silicon sensors
-> Zhenyu: requested for a new quote from Hamamatsu. Partial delivery
of Silicon sensors is not possible.

3. Use thermal camera with cooling applied to the other side of the
mechanical structure to check if there is air trapped between hybrid
and MS
-> Yi: trying it this week. Consider doing this in production

4. Update the T-board design
-> Jianing will update the design this week
1) Move the capacitor to the other side
2) Add two ground holes
3) Tolerance for mounting T-board on the MS, taking into account the
constraint from connecting the outer hybrid
4) Check mounting T-board on the MS -> Yi will do it at NCKU

5. Split HV for inner and outer
-> Decided to split HV. Mike/Gerard will look into the changes to PPB
and back-of-crate boards

6. Integration
-> Rahul: will do a tolerance analysis, taking into account the
clearance/project requirements but also what can be achieved by the
machine shop. Need to have a plan for survey and discuss with Survey
group

7. Simulation
-> Gavin/Shenghui: slow simulator based on cosmic data is ready.
Trying to run the tracking code on RCF.

8. Mechanical structure
-> Yi: Han-Sheng leaving the project next week for PhD in US. Test
the new procedure with old hybrids. Will verify with the vendor about
changes to the precision pin: lead and pin lengths

***** Action items *****
1) Design and fabricate light-tight box for the DAQ integration test
at BNL - Rahul/Flemming
2) Design the cooling lines, and cable trays between disks and
cooling manifold - Felix/Rahul
3) Finalize how to mount modules onto the half-rings, and half-rings
onto support structure, and document the proposed changes to the
mechanical structure - Rahul/Yi/Zhenyu
4) Survey procedure/requirements - Rahul

5) Prepare documents for prelim Safety review with C-AD - all
6) Get updated quote from Hamamatsu - Zhenyu
7) Design and fabricate module storage boxes for production at UIC -
Xu/Andres
8) Duplicate the module assembly tooling at UIC - Xu/Zhenyu
9) Discuss with Fermilab about module assembly schedule - Zhenyu

10) Update the T-board design to avoid the conflict with Mechanical
structure - Jianing/Maowu
11) Check how T-board mount onto MS - Yi

12) Look into splitting the inner and outer sensor HV bias -
Mike/Gerard
13) Send the problematic prototype cable-T-board assembly to Mike for
investigation - Zhenyu/Mike
14) Develop the QC procedure for Inner cable and T-board assembly -
Mike/Maowu

15) Look into the overall large CMN noise, and the abnormal noise of
few channels first appear in the readout - Gerard/Xu
16) Check the FST noise performance at high readout rate - Xu/Zhenyu
17) Sett up the laser test stand to characterize prototype module
performance - Andres/Zhenyu
18) FST slow simulator with efficiency/resolution measured with
prototypes and study tracking performance - Gavin/Shenghui

On Aug 8, 2020, at 10:48 AM, Ye, Zhenyu <yezhenyu AT uic.edu> wrote:

Dear all,

We will have the Weekly FST meeting on Monday starting at 9am EST
(BNL local time).

Bluejeans Meeting URL https://bluejeans.com/101020434 Meeting ID:
101 020 434

https://drupal.star.bnl.gov/STAR/event/2020/08/10/star-forward-silic
on-tracker-meeting

0. follow-ups on review and action items
1. Integration
by Rahul Sharma, Felix Archampong
2. Hybrid and T-board by
Maowu Nie, Jianing Dong
3. Simulation Studies
by Gavin Wilks, Shenghui Zhang, Daniel Brandenburg
4. Prototype Module Assembly and Test by Zhenyu
Ye
5. Mechanical structure
by Yi Yang
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--
Flemming Videbaek
senior scientist
videbaek @ bnl.gov
Brookhaven National Lab
Physics Department
Bldg 510D
Upton, NY 11973

phone: 631-344-4106
cell : 631-681-1596
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Re: [Star-fst-l] Weekly FST meeting, August 10 9am (BNL time) , (continued)